[PATCH] D36498: [InstCombine] Teach foldSelectICmpAnd to recognize a (icmp slt trunc X, 0) and (icmp sgt trunc X, -1) as equivalent to an and with the sign bit of the truncated type

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In https://reviews.llvm.org/D36498#846103, @craig.topper wrote:

> I believe the issue is that this needs to handle And slightly differently. I think if MaskedValueIsZero returns true for the And, we should reset the BitsToClear to 0 before returning true.
>
>   // If the operation is an AND/OR/XOR and the bits to clear are zero in the
>   // other side, BitsToClear is ok.
>   if (Tmp == 0 && I->isBitwiseLogicOp()) {
>     // We use MaskedValueIsZero here for generality, but the case we care
>     // about the most is constant RHS.
>     unsigned VSize = V->getType()->getScalarSizeInBits();
>     if (IC.MaskedValueIsZero(I->getOperand(1),
>                              APInt::getHighBitsSet(VSize, BitsToClear),
>                              0, CxtI))
>       return true;
>   }
>   


Looks like that problem will be fixed in https://reviews.llvm.org/D36944. I think that will make this one good, but please update after that.

I'm still trying to get the backend prepared for IR to go in the other direction with patches like https://reviews.llvm.org/D36840.


https://reviews.llvm.org/D36498