[PATCH] D36893: [AArch64] Custom lowering of copysign f16

[Oliver Stannard via Phabricator via llvm-commits]

olista01 added inline comments.


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:4082
+  if (SrcVT.bitsLT(VT) &&
+      !(In2.getValueType() == MVT::f16 && Subtarget->hasFullFP16()))
     In2 = DAG.getNode(ISD::FP_EXTEND, DL, VT, In2);
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Why does this need a special case for f16?


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:4116
+    setVecVal(AArch64::dsub);
+  } else if (VT == MVT::f16) {
+    EltMask = 0x8000ULL;
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We could also do this for v4f16 and v8f16.


https://reviews.llvm.org/D36893