[PATCH] D36795: [SystemZ] Increase number of LOCRs emitted by passing regalloc hints

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa added a comment.

I experimented a bit and found that by forcing the AllocationOrder to only return hints ("hard hints"), resulted in only 3 jump/sequence expansions on SPEC. It seems that those remaining cases are due to complex cases like:

  1 LOCRMux  V0_GRX32, V1_GR32
  2 LOCRMux  VO_GRX32, V2_GRX32
  
  V2 gest assigned to GRH32
  ...

The reason this is not handled by the regclass constraining in emitSelect() is that the reg-coalescer introduced the V1_GR32, while it was originally a GRX32 during isel.
This is also what would happen if V2 was GRH32, although that is practically not happening currently (3 cases in total during isel).

I think that to handle those cases we would have to constrain regclasses somehow after coalescing. And maybe better than giving hard hints would be to immediately after one out of two GRX32 regs gets allocated constrain the other virtreg.

I am not convinced still that making this guarantee generally is possible (without a target pre-ra pass to do this), especially not for all different kind of register allocators that are around / may appear. It seems that some kind of broader construct is needed in order to always be sure this never goes wrong. Maybe a property of a register class somehow that all operands of any MI must belong to one out of two sub regclasses...? :-/

Since there are more GRX32 constructs to implement in the SystemZ backend, this may still be worthwhile, or?


https://reviews.llvm.org/D36795