[PATCH] D35241: [DAGCombine] Fix for shuffle to vector extend for non power 2 vectors

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

I don't have time to finish this off, but this further reduced version of the test case appears to still show the same issue - please can you confirm (and possibly see if you further reduce it)?

  define amdgpu_ps void @main() local_unnamed_addr {
  .entry:
    br i1 undef, label %bb12, label %bb
  
  bb:
    %tmp = tail call float @llvm.fma.f32(float undef, float 2.000000e+00, float -1.000000e+00)
    %tmp2 = bitcast float %tmp to i32
    %__llpc_global_proxy_r5.12.vec.insert = insertelement <4 x i32> undef, i32 %tmp2, i32 3
    %tmp3 = shufflevector <4 x i32> %__llpc_global_proxy_r5.12.vec.insert, <4 x i32> undef, <3 x i32> <i32 undef, i32 undef, i32 1>
    %tmp4 = bitcast <3 x i32> %tmp3 to <3 x float>
    %a2.i123 = extractelement <3 x float> %tmp4, i32 2
    %v2.i101 = fmul float %a2.i123, %a2.i123
    %tmp5 = bitcast float %v2.i101 to i32
    %__llpc_global_proxy_r2.0.vec.insert196 = insertelement <4 x i32> undef, i32 %tmp5, i32 0
    br label %bb12
  
  bb12:
    %__llpc_global_proxy_r2.0 = phi <4 x i32> [ %__llpc_global_proxy_r2.0.vec.insert196, %bb ], [ undef, %.entry ]
    %tmp6 = shufflevector <4 x i32> %__llpc_global_proxy_r2.0, <4 x i32> undef, <3 x i32> <i32 1, i32 2, i32 3>
    %tmp7 = bitcast <3 x i32> %tmp6 to <3 x float>
    %a0.i = extractelement <3 x float> %tmp7, i32 0
    ret void
  }
  
  declare float @llvm.fma.f32(float, float, float)


https://reviews.llvm.org/D35241