[PATCH] D36743: [InstCombine] Added support for (X >>s C) << C --> X & (-1 << C)

[Sanjay Patel via Phabricator via llvm-commits]

spatel added inline comments.


================
Comment at: test/Transforms/InstCombine/shift.ll:225-235
+define i32 @test12a(i32 %A) {
+; CHECK-LABEL: @test12a(
+; CHECK-NEXT:    [[a:%.*]] = and i32 %A, 1073741568
+; CHECK-NEXT:    [[C:%.*]] = or i32 [[a]], -1073741824
+; CHECK-NEXT:    ret i32 [[C]]
+;
+  %a = or i32 %A, -1073741824
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This test doesn't change with this patch, does it? Demanded-bits should already get this. That's why my suggested test case included an extra use of the right-shifted value.

Also, I'm not sure if your intent was to purposely show a hole in utils/update_test_checks.py, but for the sake of human readability, please don't use variables that only differ in capitalization. :)


https://reviews.llvm.org/D36743