[PATCH] D36698: IPRA: Allow target to enable IPRA by default

[Matt Arsenault via Phabricator via llvm-commits]

arsenm updated this revision to Diff 111038.
arsenm added a comment.

Move to TargetPassConfig


https://reviews.llvm.org/D36698

Files:
  include/llvm/Target/TargetMachine.h
  lib/CodeGen/TargetPassConfig.cpp
  lib/Target/TargetMachine.cpp


Index: lib/Target/TargetMachine.cpp
===================================================================
--- lib/Target/TargetMachine.cpp
+++ lib/Target/TargetMachine.cpp
@@ -31,10 +31,6 @@
 #include "llvm/Target/TargetSubtargetInfo.h"
 using namespace llvm;
 
-cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
-                         cl::desc("Enable interprocedural register allocation "
-                                  "to reduce load/store at procedure calls."));
-
 //---------------------------------------------------------------------------
 // TargetMachine Class
 //
@@ -45,8 +41,6 @@
     : TheTarget(T), DL(DataLayoutString), TargetTriple(TT), TargetCPU(CPU),
       TargetFS(FS), AsmInfo(nullptr), MRI(nullptr), MII(nullptr), STI(nullptr),
       RequireStructuredCFG(false), DefaultOptions(Options), Options(Options) {
-  if (EnableIPRA.getNumOccurrences())
-    this->Options.EnableIPRA = EnableIPRA;
 }
 
 TargetMachine::~TargetMachine() {
Index: lib/CodeGen/TargetPassConfig.cpp
===================================================================
--- lib/CodeGen/TargetPassConfig.cpp
+++ lib/CodeGen/TargetPassConfig.cpp
@@ -47,6 +47,9 @@
 
 using namespace llvm;
 
+cl::opt<bool> EnableIPRA("enable-ipra", cl::init(false), cl::Hidden,
+                         cl::desc("Enable interprocedural register allocation "
+                                  "to reduce load/store at procedure calls."));
 static cl::opt<bool> DisablePostRASched("disable-post-ra", cl::Hidden,
     cl::desc("Disable Post Regalloc Scheduler"));
 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
@@ -362,6 +365,13 @@
   if (StringRef(PrintMachineInstrs.getValue()).equals(""))
     TM.Options.PrintMachineCode = true;
 
+  if (EnableIPRA.getNumOccurrences())
+    TM.Options.EnableIPRA = EnableIPRA;
+  else {
+    // If not explicitly specified, use target default.
+    TM.Options.EnableIPRA = TM.useIPRA();
+  }
+
   if (TM.Options.EnableIPRA)
     setRequiresCodeGenSCCOrder();
 
Index: include/llvm/Target/TargetMachine.h
===================================================================
--- include/llvm/Target/TargetMachine.h
+++ include/llvm/Target/TargetMachine.h
@@ -259,6 +259,10 @@
   /// PEI. If false (virtual-register machines), then callee-save register
   /// spilling and scavenging are not needed or used.
   virtual bool usesPhysRegsForPEI() const { return true; }
+
+  virtual bool useIPRA() const {
+    return false;
+  }
 };
 
 /// This class describes a target machine that is implemented with the LLVM


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D36698.111038.patch
Type: text/x-patch
Size: 2571 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170814/38deed35/attachment.bin>