[PATCH] D36654: [X86] Correct two places that seemed to be mishandling X86ISD::UMUL

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.

According to the X86ISelLowering.h, UMUL results are low, high, and flags. But one place was treating result 1 as flags, and another place was treating result 1 or 2 as flags.


https://reviews.llvm.org/D36654

Files:
  lib/Target/X86/X86ISelLowering.cpp


Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -17604,7 +17604,7 @@
     return true;
   if (Op.getResNo() == 1 &&
       (Opc == X86ISD::ADD || Opc == X86ISD::SUB || Opc == X86ISD::ADC ||
-       Opc == X86ISD::SBB || Opc == X86ISD::SMUL || Opc == X86ISD::UMUL ||
+       Opc == X86ISD::SBB || Opc == X86ISD::SMUL ||
        Opc == X86ISD::INC || Opc == X86ISD::DEC || Opc == X86ISD::OR ||
        Opc == X86ISD::XOR || Opc == X86ISD::AND))
     return true;
@@ -26915,12 +26915,15 @@
   Known.resetAll();
   switch (Opc) {
   default: break;
+  case X86ISD::UMUL:
+    if (Op.getResNo() == 2)
+      goto bool_result;
+    break;
   case X86ISD::ADD:
   case X86ISD::SUB:
   case X86ISD::ADC:
   case X86ISD::SBB:
   case X86ISD::SMUL:
-  case X86ISD::UMUL:
   case X86ISD::INC:
   case X86ISD::DEC:
   case X86ISD::OR:
@@ -26931,6 +26934,7 @@
       break;
     LLVM_FALLTHROUGH;
   case X86ISD::SETCC:
+bool_result:
     Known.Zero.setBitsFrom(1);
     break;
   case X86ISD::MOVMSK: {


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