[PATCH] D36638: [AVX512] Correct isExtractSubvectorCheap so that it will return true for extracting 128-bits from the upper 256-bits of a 512-bit vector

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 110859.
craig.topper added a comment.

Update to include the correct answer for mask registers. Which seems to be that will allow any extract of a 0 index and otherwise only extracts of upper half.


https://reviews.llvm.org/D36638

Files:
  lib/Target/X86/X86ISelLowering.cpp


Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -4579,7 +4579,13 @@
   if (!isOperationLegalOrCustom(ISD::EXTRACT_SUBVECTOR, ResVT))
     return false;
 
-  return (Index == 0 || Index == ResVT.getVectorNumElements());
+  // Mask vectors support all subregister combinations and operations that
+  // extract half of vector.
+  if (ResVT.getVectorElementType() == MVT::i1)
+    return Index = 0 || ((ResVT.getSizeInBits() == SrcVT.getSizeInBits() * 2) &&
+                         (Index == ResVT.getVectorNumElements()));
+
+  return (Index % ResVT.getVectorNumElements()) == 0;
 }
 
 bool X86TargetLowering::isCheapToSpeculateCttz() const {


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