[PATCH] D36518: [SLPVectorizer] Schedule bundle with different opcodes.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Thanks for the new tests - a few minor remarks.



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Comment at: test/Transforms/SLPVectorizer/X86/schedul_bundel.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -slp-vectorizer -slp-vectorizer -mcpu=bdver1 < %s | FileCheck %s
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typo - please rename the test file schedule-bundle.ll


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Comment at: test/Transforms/SLPVectorizer/X86/schedul_bundel.ll:28
+; CHECK-NEXT:    [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[ADD7]], i32 3
+; CHECK-NEXT:    ret <4 x float> [[VECINIT3_I]]
+;
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This test doesn't seem to be working?


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Comment at: test/Transforms/SLPVectorizer/X86/schedul_bundel.ll:91
+  store i32 %.lobit.not.5, i32* getelementptr ([1 x i32], [1 x i32]* @a, i64 5, i64 0), align 4, !tbaa !2
+  store i32 6, i32* @c, align 4, !tbaa !2
+  ret i32 undef
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What is this constant store for?


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Comment at: test/Transforms/SLPVectorizer/X86/schedul_bundel.ll:99
+!4 = !{!"omnipotent char", !5, i64 0}
+!5 = !{!""}
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You can drop these attributes if you remove the (unnecessary) tbaa tags


https://reviews.llvm.org/D36518