[llvm] r310713 - [mips] Lift the assertion on the types that can be used with MipsGPRel
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 11 07:36:06 PDT 2017
Author: sdardis
Date: Fri Aug 11 07:36:05 2017
New Revision: 310713
URL: http://llvm.org/viewvc/llvm-project?rev=310713&view=rev
Log:
[mips] Lift the assertion on the types that can be used with MipsGPRel
Post commit review of rL308619 highlighted the need for handling N64
with -fno-pic. Testing reveale a stale assert when generating a GP
relative addressing mode.
This patch removes that assert and adds the necessary patterns for
MIPS64 to perform gp relative addressing with -fno-pic
(and the implicit -mno-abicalls + -mgpopt).
Reviewers: atanasyan, nitesh.jain
Differential Revision: https://reviews.llvm.org/D36472
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.h
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=310713&r1=310712&r2=310713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Fri Aug 11 07:36:05 2017
@@ -610,6 +610,12 @@ multiclass MipsHighestHigherHiLoRelocs<I
let AdditionalPredicates = [NotInMicroMips] in
defm : MipsHighestHigherHiLoRelocs<LUi64, DADDiu>, SYM_64;
+// gp_rel relocs
+def : MipsPat<(add GPR64:$gp, (MipsGPRel tglobaladdr:$in)),
+ (DADDiu GPR64:$gp, tglobaladdr:$in)>, ABI_N64;
+def : MipsPat<(add GPR64:$gp, (MipsGPRel tconstpool:$in)),
+ (DADDiu GPR64:$gp, tconstpool:$in)>, ABI_N64;
+
def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
def : WrapperPat<tconstpool, DADDiu, GPR64>;
def : WrapperPat<texternalsym, DADDiu, GPR64>;
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=310713&r1=310712&r2=310713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Aug 11 07:36:05 2017
@@ -2057,7 +2057,7 @@ SDValue MipsTargetLowering::lowerGlobalA
const GlobalObject *GO = GV->getBaseObject();
if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine()))
// %gp_rel relocation
- return getAddrGPRel(N, SDLoc(N), Ty, DAG);
+ return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
// %hi/%lo relocation
return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
@@ -2212,7 +2212,7 @@ lowerConstantPool(SDValue Op, SelectionD
if (TLOF->IsConstantInSmallSection(DAG.getDataLayout(), N->getConstVal(),
getTargetMachine()))
// %gp_rel relocation
- return getAddrGPRel(N, SDLoc(N), Ty, DAG);
+ return getAddrGPRel(N, SDLoc(N), Ty, DAG, ABI.IsN64());
return Subtarget.hasSym32() ? getAddrNonPIC(N, SDLoc(N), Ty, DAG)
: getAddrNonPICSym64(N, SDLoc(N), Ty, DAG);
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=310713&r1=310712&r2=310713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Fri Aug 11 07:36:05 2017
@@ -475,13 +475,12 @@ class TargetRegisterClass;
// (add $gp, %gp_rel(sym))
template <class NodeTy>
SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
- SelectionDAG &DAG) const {
- assert(Ty == MVT::i32);
+ SelectionDAG &DAG, bool IsN64) const {
SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
- return DAG.getNode(ISD::ADD, DL, Ty,
- DAG.getRegister(Mips::GP, Ty),
- DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty),
- GPRel));
+ return DAG.getNode(
+ ISD::ADD, DL, Ty,
+ DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
+ DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
}
/// This function fills Ops, which is the list of operands that will later
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=310713&r1=310712&r2=310713&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Aug 11 07:36:05 2017
@@ -220,6 +220,8 @@ def IsSym32 : Predicate<"Subtarg
AssemblerPredicate<"FeatureSym32">;
def IsSym64 : Predicate<"!Subtarget->HasSym32()">,
AssemblerPredicate<"!FeatureSym32">;
+def IsN64 : Predicate<"Subtarget->isABI_N64()">;
+def IsNotN64 : Predicate<"!Subtarget->isABI_N64()">;
def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">;
def RelocPIC : Predicate<"TM.isPositionIndependent()">;
def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
@@ -401,6 +403,16 @@ class MADD4 {
list<Predicate> AdditionalPredicates = [HasMadd4];
}
+// Classses used for separating expansions that differ based on the ABI in
+// use.
+class ABI_N64 {
+ list<Predicate> AdditionalPredicates = [IsN64];
+}
+
+class ABI_NOT_N64 {
+ list<Predicate> AdditionalPredicates = [IsNotN64];
+}
+
//===----------------------------------------------------------------------===//
class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
@@ -2748,9 +2760,9 @@ def : MipsPat<(MipsGotHi texternalsym:$i
// gp_rel relocs
def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
- (ADDiu GPR32:$gp, tglobaladdr:$in)>;
+ (ADDiu GPR32:$gp, tglobaladdr:$in)>, ABI_NOT_N64;
def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
- (ADDiu GPR32:$gp, tconstpool:$in)>;
+ (ADDiu GPR32:$gp, tconstpool:$in)>, ABI_NOT_N64;
// wrapper_pic
class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
Modified: llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll?rev=310713&r1=310712&r2=310713&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll Fri Aug 11 07:36:05 2017
@@ -1,14 +1,33 @@
-; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 \
+; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 -verify-machineinstrs \
; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt \
-; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON
-; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 \
+; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON,ADDR32
+; RUN: llc < %s -march=mips -mcpu=mips32 -mips-ssection-threshold=8 -verify-machineinstrs \
; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt -membedded-data \
-; RUN: | FileCheck %s --check-prefixes=EMBDATA,COMMON
+; RUN: | FileCheck %s --check-prefixes=EMBDATA,COMMON,ADDR32
+
+; RUN: llc < %s -march=mips64 -mcpu=mips4 -mips-ssection-threshold=8 -verify-machineinstrs \
+; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt -target-abi n64 \
+; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON,N64
+; RUN: llc < %s -march=mips64 -mcpu=mips4 -mips-ssection-threshold=8 -verify-machineinstrs \
+; RUN: -relocation-model=static -mattr=+noabicalls,+sym32 -mgpopt -target-abi n64 \
+; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON,N64
+; RUN: llc < %s -march=mips64 -mcpu=mips4 -mips-ssection-threshold=8 -verify-machineinstrs \
+; RUN: -relocation-model=static -mattr=+noabicalls -mgpopt -target-abi n32 \
+; RUN: | FileCheck %s --check-prefixes=BASIC,COMMON,ADDR32
; Test the layout of objects when compiling for static, noabicalls environment.
%struct.anon = type { i32, i32 }
+; Check that when synthesizing a pointer to the second element of foo, that
+; we use the correct addition operation. O32 and N32 have 32-bit address
+; spaces, so they use addiu. N64 has a 64bit address space, but has a submode
+; where symbol sizes are 32 bits. In those cases we use daddiu.
+
+; CHECK-LABEL: A1:
+; N64: daddiu ${{[0-9]+}}, $gp, %gp_rel(foo)
+; ADDR32: addiu ${{[0-9]+}}, $gp, %gp_rel(foo)
+
; BASIC: .type s0, at object
; BASIC-NEXT: .section .sdata,"aw", at progbits
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