[llvm] r310575 - [AArch64] Assembler support for v8.3 RCpc
Sam Parker via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 10 02:52:55 PDT 2017
Author: sam_parker
Date: Thu Aug 10 02:52:55 2017
New Revision: 310575
URL: http://llvm.org/viewvc/llvm-project?rev=310575&view=rev
Log:
[AArch64] Assembler support for v8.3 RCpc
Added assembler and disassembler support for the new Release
Consistent processor consistent instructions, introduced with ARM
v8.3-A for AArch64.
Differential Revision: https://reviews.llvm.org/D36522
Added:
llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
Modified:
llvm/trunk/lib/Target/AArch64/AArch64.td
llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=310575&r1=310574&r2=310575&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Thu Aug 10 02:52:55 2017
@@ -118,6 +118,9 @@ def FeatureDisableLatencySchedHeuristic
"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
"Disable latency scheduling heuristic">;
+def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
+ "Enable support for RCPC extension">;
+
def FeatureUseRSqrt : SubtargetFeature<
"use-reciprocal-square-root", "UseRSqrt", "true",
"Use the reciprocal square root approximation">;
@@ -147,7 +150,7 @@ def HasV8_2aOps : SubtargetFeature<"v8.2
"Support ARM v8.2a instructions", [HasV8_1aOps, FeatureRAS]>;
def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
- "Support ARM v8.3a instructions", [HasV8_2aOps]>;
+ "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC]>;
//===----------------------------------------------------------------------===//
// Register File Description
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=310575&r1=310574&r2=310575&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Thu Aug 10 02:52:55 2017
@@ -1098,6 +1098,18 @@ class SpecialReturn<bits<4> opc, string
let Inst{9-5} = 0b11111;
}
+let mayLoad = 1 in
+class RCPCLoad<bits<2> sz, string asm, RegisterClass RC>
+ : I<(outs RC:$Rt), (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]", "", []>,
+ Sched<[]> {
+ bits<5> Rn;
+ bits<5> Rt;
+ let Inst{31-30} = sz;
+ let Inst{29-10} = 0b11100010111111110000;
+ let Inst{9-5} = Rn;
+ let Inst{4-0} = Rt;
+}
+
//---
// Conditional branch instruction.
//---
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=310575&r1=310574&r2=310575&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Thu Aug 10 02:52:55 2017
@@ -46,6 +46,8 @@ def HasFuseAES : Predicate<"Subtar
"fuse-aes">;
def HasSVE : Predicate<"Subtarget->hasSVE()">,
AssemblerPredicate<"FeatureSVE", "sve">;
+def HasRCPC : Predicate<"Subtarget->hasRCPC()">,
+ AssemblerPredicate<"FeatureRCPC", "rcpc">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
@@ -448,6 +450,14 @@ def UDOTIDX4S : BaseSIMDThreeSameVectorD
def SDOTIDX4S : BaseSIMDThreeSameVectorDotIndex<1, 0, "sdot", ".4s", ".16b", ".4b">;
}
+let Predicates = [HasRCPC] in {
+ // v8.3 Release Consistent Processor Consistent support
+ def LDAPRB : RCPCLoad<0b00, "ldaprb", GPR32>;
+ def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>;
+ def LDAPRW : RCPCLoad<0b10, "ldapr", GPR32>;
+ def LDAPRX : RCPCLoad<0b11, "ldapr", GPR64>;
+}
+
def : InstAlias<"clrex", (CLREX 0xf)>;
def : InstAlias<"isb", (ISB 0xf)>;
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=310575&r1=310574&r2=310575&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Thu Aug 10 02:52:55 2017
@@ -73,6 +73,7 @@ protected:
bool HasSPE = false;
bool HasLSLFast = false;
bool HasSVE = false;
+ bool HasRCPC = false;
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
bool HasZeroCycleRegMove = false;
@@ -257,6 +258,7 @@ public:
bool hasSPE() const { return HasSPE; }
bool hasLSLFast() const { return HasLSLFast; }
bool hasSVE() const { return HasSVE; }
+ bool hasRCPC() const { return HasRCPC; }
bool isLittleEndian() const { return IsLittle; }
Added: llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s?rev=310575&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.3a-rcpc.s Thu Aug 10 02:52:55 2017
@@ -0,0 +1,23 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.3a < %s 2>&1 | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a < %s 2> %t
+// RUN: FileCheck --check-prefix=CHECK-REQ %s < %t
+
+ ldaprb w0, [x0, #0]
+ ldaprh w0, [x17, #0]
+ ldapr w0, [x1, #0]
+ ldapr x0, [x0, #0]
+ ldapr w18, [x0]
+ ldapr x15, [x0]
+
+// CHECK: ldaprb w0, [x0] // encoding: [0x00,0xc0,0xbf,0x38]
+// CHECK: ldaprh w0, [x17] // encoding: [0x20,0xc2,0xbf,0x78]
+// CHECK: ldapr w0, [x1] // encoding: [0x20,0xc0,0xbf,0xb8]
+// CHECK: ldapr x0, [x0] // encoding: [0x00,0xc0,0xbf,0xf8]
+// CHECK: ldapr w18, [x0] // encoding: [0x12,0xc0,0xbf,0xb8]
+// CHECK: ldapr x15, [x0] // encoding: [0x0f,0xc0,0xbf,0xf8]
+// CHECK-REQ: error: invalid operand for instruction
+// CHECK-REQ: error: invalid operand for instruction
+// CHECK-REQ: error: invalid operand for instruction
+// CHECK-REQ: error: invalid operand for instruction
+// CHECK-REQ: error: instruction requires: rcpc
+// CHECK-REQ: error: instruction requires: rcpc
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt?rev=310575&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.3a-rcpc.txt Thu Aug 10 02:52:55 2017
@@ -0,0 +1,26 @@
+# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.3a --disassemble < %s | FileCheck %s
+
+# CHECK: ldaprb w0, [x0]
+# CHECK: ldaprh w0, [x0]
+# CHECK: ldapr w0, [x0]
+# CHECK: ldapr x0, [x0]
+[0x00,0xc0,0xbf,0x38]
+[0x00,0xc0,0xbf,0x78]
+[0x00,0xc0,0xbf,0xb8]
+[0x00,0xc0,0xbf,0xf8]
+
+# RUN: not llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s 2>&1 | FileCheck --check-prefix=CHECK-V8_2A %s
+
+# CHECK-V8_2A: warning: invalid instruction encoding
+# CHECK-V8_2A: [0x00,0xc0,0xbf,0x38]
+# CHECK-V8_2A: ^
+# CHECK-V8_2A: warning: invalid instruction encoding
+# CHECK-V8_2A: [0x00,0xc0,0xbf,0x78]
+# CHECK-V8_2A: ^
+# CHECK-V8_2A: warning: invalid instruction encoding
+# CHECK-V8_2A: [0x00,0xc0,0xbf,0xb8]
+# CHECK-V8_2A: ^
+# CHECK-V8_2A: warning: invalid instruction encoding
+# CHECK-V8_2A: [0x00,0xc0,0xbf,0xf8]
+# CHECK-V8_2A: ^
+
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