[PATCH] D34569: [DAG] Relax type restriction for store merge

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12487
+              Val = DAG.getConstant(
+                  (uint32_t)CFP->getValueAPF().bitcastToAPInt().getZExtValue(),
+                  SDLoc(CFP), IntMemVT);
----------------
Why isn't this CFP->getValueAPF().bitcastToAPInt().zextOrTrunc(8 * ElementSizeBytes) ?


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12638
+      if (MemVT.isInteger() ? !MemVT.bitsEq(Other->getMemoryVT())
+                            : Other->getMemoryVT() != MemVT)
         return false;
----------------
Pull the ternary operator out of the if()


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12665
+      if (Val.getOpcode() != ISD::EXTRACT_VECTOR_ELT &&
+          Val.getOpcode() != ISD::EXTRACT_SUBVECTOR)
         return false;
----------------
NFC change


https://reviews.llvm.org/D34569