[PATCH] D36511: [SelectionDAG] When scalarizing vselect, don't assert on a legal cond operand.

[Elad Cohen via Phabricator via llvm-commits]

eladcohen created this revision.

When scalarizing the result of a vselect, the legalizer currently expects
to already have scalarized the operands. While this is true for the true/false
operands (which have the same type as the result), it is not case for the
condition operand. On X86 AVX512, v1i1 is legal - this leads to operations such
as '< N x type> vselect < N x i1> < N x type> < N x type>' where < N x type > is
illegal to hit an assertion during the scalarization.

The handling is similar to r205625.
This also exposes the fact that (v1i1 extract_subvector) should be legal
and selectable on AVX512 - We do this by custom lowering to vector_extract_elt.
This still leaves us in some cases with redundant dag nodes which will be
combined in a separate soon to come patch.

This fixes pr33349.


https://reviews.llvm.org/D36511

Files:
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/pr33349.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D36511.110361.patch
Type: text/x-patch
Size: 6146 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170809/aad8b5a6/attachment.bin>