[PATCH] D23563: [RISCV 6/10] Add basic RISCVAsmParser

[Alex Bradbury via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL310361: [RISCV] Add basic RISCVAsmParser (authored by asb).

Changed prior to commit:
  https://reviews.llvm.org/D23563?vs=88305&id=110198#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D23563

Files:
  llvm/trunk/lib/Target/RISCV/CMakeLists.txt
  llvm/trunk/lib/Target/RISCV/LLVMBuild.txt
  llvm/trunk/lib/Target/RISCV/RISCV.td
  llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td


Index: llvm/trunk/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCV.td
+++ llvm/trunk/lib/Target/RISCV/RISCV.td
@@ -22,6 +22,11 @@
 
 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
 
+def RISCVAsmParser : AsmParser {
+  let ShouldEmitMatchRegisterAltName = 1;
+}
+
 def RISCV : Target {
   let InstructionSet = RISCVInstrInfo;
+  let AssemblyParsers = [RISCVAsmParser];
 }
Index: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
@@ -13,7 +13,16 @@
 
 include "RISCVInstrFormats.td"
 
-def simm12 : Operand<i32>;
+class SImmAsmOperand<int width>
+  : AsmOperandClass {
+  let Name = "SImm" # width;
+  let RenderMethod = "addImmOperands";
+  let DiagnosticType = !strconcat("Invalid", Name);
+}
+
+def simm12 : Operand<i32> {
+  let ParserMatchClass = SImmAsmOperand<12>;
+}
 
 // As noted in RISCVRegisterInfo.td, the hope is that support for
 // variable-sized register classes will mean that instruction definitions do
Index: llvm/trunk/lib/Target/RISCV/LLVMBuild.txt
===================================================================
--- llvm/trunk/lib/Target/RISCV/LLVMBuild.txt
+++ llvm/trunk/lib/Target/RISCV/LLVMBuild.txt
@@ -16,12 +16,13 @@
 ;===------------------------------------------------------------------------===;
 
 [common]
-subdirectories = TargetInfo MCTargetDesc
+subdirectories = AsmParser TargetInfo MCTargetDesc
 
 [component_0]
 type = TargetGroup
 name = RISCV
 parent = Target
+has_asmparser = 1
 
 [component_1]
 type = Library
Index: llvm/trunk/lib/Target/RISCV/CMakeLists.txt
===================================================================
--- llvm/trunk/lib/Target/RISCV/CMakeLists.txt
+++ llvm/trunk/lib/Target/RISCV/CMakeLists.txt
@@ -3,12 +3,14 @@
 tablegen(LLVM RISCVGenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM RISCVGenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM RISCVGenMCCodeEmitter.inc -gen-emitter)
+tablegen(LLVM RISCVGenAsmMatcher.inc -gen-asm-matcher)
 
 add_public_tablegen_target(RISCVCommonTableGen)
 
 add_llvm_target(RISCVCodeGen
   RISCVTargetMachine.cpp
   )
 
+add_subdirectory(AsmParser)
 add_subdirectory(TargetInfo)
 add_subdirectory(MCTargetDesc)


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D23563.110198.patch
Type: text/x-patch
Size: 2388 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170808/e09807ac/attachment.bin>