[PATCH] D36055: [X86] Disable creating BEXTR from shift and mask operations with BMI. Only do it for TBM.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.

The BMI version of BEXTR takes a bit count and shift value packed into a register. TBM passes it as an immediate. Currently we have a DAG combine that creates BEXTR from shift and mask if either BMI or TBM is supported.

For the BMI case this means we have to move the immediate into a register first and then do the BEXTR. So its always 2 instructions. The shift and mask we replaced would have also been 2 instructions. On Intel hardware, BEXTR is 2 uops according to Agner Fog's tables so that means we probably went from 2 uops to do shift and mask, to 3 uops to move the immediate and do the BEXTR. So I doubt this is a win.

This patch disables the combine for BMI and leaves it only for TBM.

I'm trying to figure out if we can move the TBM version to isel as we are currently using BEXTR when we could zero extend AH/BH/CH/DH. The latter is handled by isel patterns while the BEXTR is handled as a DAG combine.


https://reviews.llvm.org/D36055

Files:
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86InstrInfo.td
  test/CodeGen/X86/bmi.ll


Index: test/CodeGen/X86/bmi.ll
===================================================================
--- test/CodeGen/X86/bmi.ll
+++ test/CodeGen/X86/bmi.ll
@@ -302,8 +302,9 @@
 define i32 @bextr32b(i32 %x)  uwtable  ssp {
 ; CHECK-LABEL: bextr32b:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movl $3076, %eax # imm = 0xC04
-; CHECK-NEXT:    bextrl %eax, %edi, %eax
+; CHECK-NEXT:    shrl $4, %edi
+; CHECK-NEXT:    andl $4095, %edi # imm = 0xFFF
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %1 = lshr i32 %x, 4
   %2 = and i32 %1, 4095
@@ -313,8 +314,9 @@
 define i32 @bextr32b_load(i32* %x)  uwtable  ssp {
 ; CHECK-LABEL: bextr32b_load:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movl $3076, %eax # imm = 0xC04
-; CHECK-NEXT:    bextrl %eax, (%rdi), %eax
+; CHECK-NEXT:    movl (%rdi), %eax
+; CHECK-NEXT:    shrl $4, %eax
+; CHECK-NEXT:    andl $4095, %eax # imm = 0xFFF
 ; CHECK-NEXT:    retq
   %1 = load i32, i32* %x
   %2 = lshr i32 %1, 4
@@ -336,8 +338,9 @@
 define i64 @bextr64b(i64 %x)  uwtable  ssp {
 ; CHECK-LABEL: bextr64b:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movl $3076, %eax # imm = 0xC04
-; CHECK-NEXT:    bextrl %eax, %edi, %eax
+; CHECK-NEXT:    shrl $4, %edi
+; CHECK-NEXT:    andl $4095, %edi # imm = 0xFFF
+; CHECK-NEXT:    movq %rdi, %rax
 ; CHECK-NEXT:    retq
   %1 = lshr i64 %x, 4
   %2 = and i64 %1, 4095
@@ -347,8 +350,9 @@
 define i64 @bextr64b_load(i64* %x) {
 ; CHECK-LABEL: bextr64b_load:
 ; CHECK:       # BB#0:
-; CHECK-NEXT:    movl $3076, %eax # imm = 0xC04
-; CHECK-NEXT:    bextrl %eax, (%rdi), %eax
+; CHECK-NEXT:    movl (%rdi), %eax
+; CHECK-NEXT:    shrl $4, %eax
+; CHECK-NEXT:    andl $4095, %eax # imm = 0xFFF
 ; CHECK-NEXT:    retq
   %1 = load i64, i64* %x, align 8
   %2 = lshr i64 %1, 4
Index: lib/Target/X86/X86InstrInfo.td
===================================================================
--- lib/Target/X86/X86InstrInfo.td
+++ lib/Target/X86/X86InstrInfo.td
@@ -2411,17 +2411,6 @@
               (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$lz, sub_32bit))>;
 } // HasBMI2
 
-let Predicates = [HasBMI] in {
-  def : Pat<(X86bextr GR32:$src1, GR32:$src2),
-            (BEXTR32rr GR32:$src1, GR32:$src2)>;
-  def : Pat<(X86bextr (loadi32 addr:$src1), GR32:$src2),
-            (BEXTR32rm addr:$src1, GR32:$src2)>;
-  def : Pat<(X86bextr GR64:$src1, GR64:$src2),
-            (BEXTR64rr GR64:$src1, GR64:$src2)>;
-  def : Pat<(X86bextr (loadi64 addr:$src1), GR64:$src2),
-            (BEXTR64rm addr:$src1, GR64:$src2)>;
-} // HasBMI
-
 multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC,
                          X86MemOperand x86memop, Intrinsic Int,
                          PatFrag ld_frag> {
Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -32055,7 +32055,7 @@
   if (VT != MVT::i32 && VT != MVT::i64)
     return SDValue();
 
-  if (!Subtarget.hasBMI() && !Subtarget.hasTBM())
+  if (!Subtarget.hasTBM())
     return SDValue();
   if (N0.getOpcode() != ISD::SRA && N0.getOpcode() != ISD::SRL)
     return SDValue();


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