[llvm] r309476 - AMDGPU: Move INDIRECT_BASE_ADDR definition out of common files

[Tom Stellard via llvm-commits]

Author: tstellar
Date: Fri Jul 28 20:44:07 2017
New Revision: 309476

URL: http://llvm.org/viewvc/llvm-project?rev=309476&view=rev
Log:
AMDGPU: Move INDIRECT_BASE_ADDR definition out of common files

Summary: This is only used by R600.

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye

Differential Revision: https://reviews.llvm.org/D35926

Modified:
    llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.td
    llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.td
    llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.td?rev=309476&r1=309475&r2=309476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.td Fri Jul 28 20:44:07 2017
@@ -17,8 +17,6 @@ foreach Index = 0-15 in {
   def sub#Index : SubRegIndex<32, !shl(Index, 5)>;
 }
 
-def INDIRECT_BASE_ADDR : Register <"INDIRECT_BASE_ADDR">;
-
 }
 
 include "R600RegisterInfo.td"

Modified: llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.td?rev=309476&r1=309475&r2=309476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/R600RegisterInfo.td Fri Jul 28 20:44:07 2017
@@ -147,6 +147,7 @@ def PRED_SEL_OFF: R600Reg<"Pred_sel_off"
 def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;
 def PRED_SEL_ONE : R600Reg<"Pred_sel_one", 3>;
 def AR_X : R600Reg<"AR.x", 0>;
+def INDIRECT_BASE_ADDR : R600Reg <"INDIRECT_BASE_ADDR", 0>;
 
 def R600_ArrayBase : RegisterClass <"AMDGPU", [f32, i32], 32,
                           (add (sequence "ArrayBase%u", 448, 480))>;

Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=309476&r1=309475&r2=309476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Fri Jul 28 20:44:07 2017
@@ -148,7 +148,6 @@ unsigned SIRegisterInfo::reservedStackPt
 
 BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   BitVector Reserved(getNumRegs());
-  Reserved.set(AMDGPU::INDIRECT_BASE_ADDR);
 
   // EXEC_LO and EXEC_HI could be allocated and used as regular register, but
   // this seems likely to result in bugs, so I'm marking them as reserved.