[llvm] r309183 - [AArch64] Adjust the cost model for Exynos M1 and M2

Evandro Menezes via llvm-commits llvm-commits at lists.llvm.org
Wed Jul 26 14:28:15 PDT 2017


Author: evandro
Date: Wed Jul 26 14:28:15 2017
New Revision: 309183

URL: http://llvm.org/viewvc/llvm-project?rev=309183&view=rev
Log:
[AArch64] Adjust the cost model for Exynos M1 and M2

Add the information for the scalar reciprocal square root approximation.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td?rev=309183&r1=309182&r2=309183&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SchedM1.td Wed Jul 26 14:28:15 2017
@@ -380,7 +380,9 @@ def : InstRW<[M1WriteFCVT3],  (instregex
 def : InstRW<[M1WriteNEONF],  (instregex "^[FSU]CVT[AMNPZ][SU](_Int)?[SU]?[XW]?[DS]?[rds]i?")>;
 def : InstRW<[M1WriteNEONE],  (instregex "^[SU]CVTF[SU]")>;
 def : InstRW<[M1WriteNALU1],  (instregex "^FMOV[DS][ir]")>;
-def : InstRW<[M1WriteNMISC1], (instregex "^FRECPXv")>;
+def : InstRW<[M1WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev1")>;
+def : InstRW<[M1WriteNMISC1], (instregex "^FRECPXv1")>;
+def : InstRW<[M1WriteFMAC5],  (instregex "^F(RECP|RSQRT)S(16|32|64)")>;
 def : InstRW<[M1WriteS4],     (instregex "^FMOV[WX][DS](High)?r")>;
 def : InstRW<[M1WriteNEONI],  (instregex "^FMOV[DS][WX](High)?r")>;
 
@@ -446,7 +448,7 @@ def : InstRW<[M1WriteNALU1],  (instregex
 def : InstRW<[M1WriteNALU1],  (instregex "^INSv.+lane")>;
 def : InstRW<[M1WriteNALU1],  (instregex "^MOVI[Dv]")>;
 def : InstRW<[M1WriteNALU1],  (instregex "^FMOVv")>;
-def : InstRW<[M1WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev")>;
+def : InstRW<[M1WriteFCVT4],  (instregex "^[FU](RECP|RSQRT)Ev[248]")>;
 def : InstRW<[M1WriteFMAC5],  (instregex "^F(RECP|RSQRT)Sv")>;
 def : InstRW<[M1WriteNALU1],  (instregex "^REV(16|32|64)v")>;
 def : InstRW<[M1WriteNAL11],  (instregex "^TB[LX]v8i8One")>;




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