[PATCH] D35127: AMDGPU/GlobalISel: Mark 32-bit G_OR as legal

[Tom Stellard via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL309165: AMDGPU/GlobalISel: Mark 32-bit G_OR as legal (authored by tstellar).

Repository:
  rL LLVM

https://reviews.llvm.org/D35127

Files:
  llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
  llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir


Index: llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -66,6 +66,8 @@
   setAction({G_LOAD, 1, P1}, Legal);
   setAction({G_LOAD, 1, P2}, Legal);
 
+  setAction({G_OR, S32}, Legal);
+
   setAction({G_SELECT, S32}, Legal);
   setAction({G_SELECT, 1, S1}, Legal);
 
Index: llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
+++ llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
@@ -0,0 +1,21 @@
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+--- |
+  define void @test_or() { ret void }
+...
+---
+name:            test_or
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+body: |
+  bb.0:
+    liveins: %vgpr0, %vgpr1
+    ; CHECK-LABEL: name: test_or
+    ; CHECK: %2(s32) = G_OR %0, %1
+
+    %0(s32) = COPY %vgpr0
+    %1(s32) = COPY %vgpr1
+    %2(s32) = G_OR %0, %1
+...


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D35127.108346.patch
Type: text/x-patch
Size: 1215 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170726/23d700a1/attachment.bin>