[PATCH] D35700: DAGCombiner: Extend reduceBuildVecToTrunc to handle non-zero offset

Zvi Rackover via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jul 26 05:24:16 PDT 2017

zvi added inline comments.

Comment at: lib/Target/X86/X86ISelLowering.cpp:35813
+  if (!SrcVT.isSimple() ||
+      is128BitLaneCrossingShuffleMask(SrcVT.getSimpleVT(), ShuffleMask))
RKSimon wrote:
> Do we need the isSimple() test? It's handled by isShuffleMaskLegal
Then in that case i will drop it. Thanks.


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