[llvm] r308903 - AMDGPU: Fix allocating pseudo-registers

[Matt Arsenault via llvm-commits]

Hi, this should go to the 5.0 branch

> On Jul 24, 2017, at 11:06, Matt Arsenault via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> Author: arsenm
> Date: Mon Jul 24 11:06:15 2017
> New Revision: 308903
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=308903&view=rev
> Log:
> AMDGPU: Fix allocating pseudo-registers
> 
> There's no need for these to be part of a class since
> they are immediately replaced. New unreachable hit in
> existing tests.'
> 
> Modified:
>    llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
>    llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
> 
> Modified: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp?rev=308903&r1=308902&r2=308903&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp Mon Jul 24 11:06:15 2017
> @@ -297,6 +297,11 @@ void AMDGPUInstPrinter::printRegOperand(
>   case AMDGPU::FLAT_SCR_HI:
>     O << "flat_scratch_hi";
>     return;
> +  case AMDGPU::FP_REG:
> +  case AMDGPU::SP_REG:
> +  case AMDGPU::SCRATCH_WAVE_OFFSET_REG:
> +  case AMDGPU::PRIVATE_RSRC_REG:
> +    llvm_unreachable("pseudo-register should not ever be emitted");
>   default:
>     break;
>   }
> 
> Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td?rev=308903&r1=308902&r2=308903&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td Mon Jul 24 11:06:15 2017
> @@ -274,8 +274,7 @@ def VGPR_512 : RegisterTuples<[sub0, sub
> def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
>   (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
>    TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT,
> -   SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT,
> -   FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG)> {
> +   SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT)> {
>   let AllocationPriority = 7;
> }
> 
> 
> 
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