[PATCH] D35299: [AArch64] Tie source and destination operands for AESMC/AESIMC.

[Tim Northover via Phabricator via llvm-commits]

t.p.northover added a comment.

> I'm afraid that it would create problems for the assembler too, wouldn't it?

Yeah, the original causes failures in test/MC. I wonder why that wasn't spotted earlier?

Anyway, I'm not sure the "single-use" heuristic is actually what we should care about. As far as I understand AES these instructions are only ever going to be seen with single-uses in reality so optimizing for other cases is probably premature.

For out-of-order non-fused implementations the register shouldn't matter as far as I can see, which leaves in-order unfused implementations. I've got much less experience there, but don't they tend to have early forwarding to dependent instructions anyway?

So perhaps a hybrid approach where the Pattern always picks these pseudo-instructions would be best?


https://reviews.llvm.org/D35299