[llvm] r308658 - Implement LaneBitmask::getNumLanes and LaneBitmask::getHighestLane

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Thu Jul 20 12:43:19 2017
New Revision: 308658

URL: http://llvm.org/viewvc/llvm-project?rev=308658&view=rev
Log:
Implement LaneBitmask::getNumLanes and LaneBitmask::getHighestLane

This should eliminate most uses of countPopulation and Log2_32 on
the lane mask values.

Modified:
    llvm/trunk/include/llvm/MC/LaneBitmask.h
    llvm/trunk/lib/CodeGen/SplitKit.cpp
    llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp
    llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
    llvm/trunk/utils/TableGen/CodeGenRegisters.cpp

Modified: llvm/trunk/include/llvm/MC/LaneBitmask.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/LaneBitmask.h?rev=308658&r1=308657&r2=308658&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/LaneBitmask.h (original)
+++ llvm/trunk/include/llvm/MC/LaneBitmask.h Thu Jul 20 12:43:19 2017
@@ -73,6 +73,13 @@ namespace llvm {
 
     constexpr Type getAsInteger() const { return Mask; }
 
+    unsigned getNumLanes() const {
+      return countPopulation(Mask);
+    }
+    unsigned getHighestLane() const {
+      return Log2_32(Mask);
+    }
+
     static LaneBitmask getNone() { return LaneBitmask(0); }
     static LaneBitmask getAll()  { return ~LaneBitmask(0); }
     static LaneBitmask getLane(unsigned Lane) {

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=308658&r1=308657&r2=308658&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Thu Jul 20 12:43:19 2017
@@ -552,7 +552,7 @@ SlotIndex SplitEditor::buildCopy(unsigne
     if ((SubRegMask & ~LaneMask).any())
       continue;
 
-    unsigned PopCount = countPopulation(SubRegMask.getAsInteger());
+    unsigned PopCount = SubRegMask.getNumLanes();
     PossibleIndexes.push_back(Idx);
     if (PopCount > BestCover) {
       BestCover = PopCount;
@@ -583,8 +583,8 @@ SlotIndex SplitEditor::buildCopy(unsigne
 
       // Try to cover as much of the remaining lanes as possible but
       // as few of the already covered lanes as possible.
-      int Cover = countPopulation((SubRegMask & LanesLeft).getAsInteger())
-                - countPopulation((SubRegMask & ~LanesLeft).getAsInteger());
+      int Cover = (SubRegMask & LanesLeft).getNumLanes()
+                - (SubRegMask & ~LanesLeft).getNumLanes();
       if (Cover > BestCover) {
         BestCover = Cover;
         BestIdx = Idx;

Modified: llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp?rev=308658&r1=308657&r2=308658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/GCNRegPressure.cpp Thu Jul 20 12:43:19 2017
@@ -107,7 +107,7 @@ void GCNRegPressure::inc(unsigned Reg,
     assert(PrevMask < NewMask);
 
     Value[Kind == SGPR_TUPLE ? SGPR32 : VGPR32] +=
-      Sign * countPopulation((~PrevMask & NewMask).getAsInteger());
+      Sign * (~PrevMask & NewMask).getNumLanes();
 
     if (PrevMask.none()) {
       assert(NewMask.any());

Modified: llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp?rev=308658&r1=308657&r2=308658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp Thu Jul 20 12:43:19 2017
@@ -1275,8 +1275,7 @@ const TargetRegisterClass *SIRegisterInf
     return RC;
 
   // We can assume that each lane corresponds to one 32-bit register.
-  LaneBitmask::Type Mask = getSubRegIndexLaneMask(SubIdx).getAsInteger();
-  unsigned Count = countPopulation(Mask);
+  unsigned Count = getSubRegIndexLaneMask(SubIdx).getNumLanes();
   if (isSGPRClass(RC)) {
     switch (Count) {
     case 1:

Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=308658&r1=308657&r2=308658&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Thu Jul 20 12:43:19 2017
@@ -1295,9 +1295,7 @@ void CodeGenRegBank::computeSubRegLaneMa
       // Moving from a class with no subregisters we just had a single lane:
       // The subregister must be a leaf subregister and only occupies 1 bit.
       // Move the bit from the class without subregisters into that position.
-      static_assert(sizeof(Idx.LaneMask.getAsInteger()) == 4,
-                    "Change Log2_32 to a proper one");
-      unsigned DstBit = Log2_32(Idx.LaneMask.getAsInteger());
+      unsigned DstBit = Idx.LaneMask.getHighestLane();
       assert(Idx.LaneMask == LaneBitmask::getLane(DstBit) &&
              "Must be a leaf subregister");
       MaskRolPair MaskRol = { LaneBitmask::getLane(0), (uint8_t)DstBit };
@@ -1328,9 +1326,7 @@ void CodeGenRegBank::computeSubRegLaneMa
         assert(Composite->getComposites().empty());
 
         // Create Mask+Rotate operation and merge with existing ops if possible.
-        static_assert(sizeof(Composite->LaneMask.getAsInteger()) == 4,
-                      "Change Log2_32 to a proper one");
-        unsigned DstBit = Log2_32(Composite->LaneMask.getAsInteger());
+        unsigned DstBit = Composite->LaneMask.getHighestLane();
         int Shift = DstBit - SrcBit;
         uint8_t RotateLeft = Shift >= 0 ? (uint8_t)Shift
                                         : LaneBitmask::BitWidth + Shift;