[PATCH] D35689: AMDGPU: Replace i64 add/sub lowering

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.

Use VOP3 add/addc like usual.

     

This has some tradeoffs. Inline immediates fold
a little better, but other constants are worse off.
SIShrinkInstructions could be made smarter to handle
these cases.

      

This allows us to avoid selecting scalar adds where we
need to track the carry in scc and replace its users.
This makes it easier to use the carryless VALU adds.


https://reviews.llvm.org/D35689

Files:
  lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIInstructions.td
  test/CodeGen/AMDGPU/add.v2i16.ll
  test/CodeGen/AMDGPU/clamp.ll
  test/CodeGen/AMDGPU/ctpop.ll
  test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
  test/CodeGen/AMDGPU/load-global-i32.ll
  test/CodeGen/AMDGPU/lshr.v2i16.ll
  test/CodeGen/AMDGPU/mul.ll
  test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
  test/CodeGen/AMDGPU/split-scalar-i64-add.ll
  test/CodeGen/AMDGPU/sub.i16.ll
  test/CodeGen/AMDGPU/sub.ll
  test/CodeGen/AMDGPU/sub.v2i16.ll

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