[llvm] r308617 - [DAG] Optimize away degenerate INSERT_VECTOR_ELT nodes.
Nirav Dave via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 20 06:48:17 PDT 2017
Author: niravd
Date: Thu Jul 20 06:48:17 2017
New Revision: 308617
URL: http://llvm.org/viewvc/llvm-project?rev=308617&view=rev
Log:
[DAG] Optimize away degenerate INSERT_VECTOR_ELT nodes.
Summary:
Add missing vector write of vector read reduction, i.e.:
(insert_vector_elt x (extract_vector_elt x idx) idx) to x
Reviewers: spatel, RKSimon, efriedma
Reviewed By: RKSimon
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D35563
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/test/CodeGen/X86/vector-shift-ashr-256.ll
llvm/trunk/test/CodeGen/X86/vector-shift-lshr-256.ll
llvm/trunk/test/CodeGen/X86/vector-shift-shl-256.ll
llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=308617&r1=308616&r2=308617&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jul 20 06:48:17 2017
@@ -13572,6 +13572,12 @@ SDValue DAGCombiner::visitINSERT_VECTOR_
EVT VT = InVec.getValueType();
+ // Remove redundant insertions:
+ // (insert_vector_elt x (extract_vector_elt x idx) idx) -> x
+ if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
+ InVec == InVal->getOperand(0) && EltNo == InVal->getOperand(1))
+ return InVec;
+
// Check that we know which element is being inserted
if (!isa<ConstantSDNode>(EltNo))
return SDValue();
Modified: llvm/trunk/test/CodeGen/X86/vector-shift-ashr-256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shift-ashr-256.ll?rev=308617&r1=308616&r2=308617&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-shift-ashr-256.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-shift-ashr-256.ll Thu Jul 20 06:48:17 2017
@@ -708,8 +708,6 @@ define <4 x i64> @splatvar_shift_v4i64(<
;
; X32-AVX1-LABEL: splatvar_shift_v4i64:
; X32-AVX1: # BB#0:
-; X32-AVX1-NEXT: vpextrd $1, %xmm1, %eax
-; X32-AVX1-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X32-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,2147483648,0,2147483648]
; X32-AVX1-NEXT: vpsrlq %xmm1, %xmm2, %xmm2
; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
@@ -724,8 +722,6 @@ define <4 x i64> @splatvar_shift_v4i64(<
;
; X32-AVX2-LABEL: splatvar_shift_v4i64:
; X32-AVX2: # BB#0:
-; X32-AVX2-NEXT: vpextrd $1, %xmm1, %eax
-; X32-AVX2-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X32-AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,2147483648,0,2147483648,0,2147483648,0,2147483648]
; X32-AVX2-NEXT: vpsrlq %xmm1, %ymm2, %ymm2
; X32-AVX2-NEXT: vpsrlq %xmm1, %ymm0, %ymm0
Modified: llvm/trunk/test/CodeGen/X86/vector-shift-lshr-256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shift-lshr-256.ll?rev=308617&r1=308616&r2=308617&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-shift-lshr-256.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-shift-lshr-256.ll Thu Jul 20 06:48:17 2017
@@ -562,8 +562,6 @@ define <4 x i64> @splatvar_shift_v4i64(<
;
; X32-AVX1-LABEL: splatvar_shift_v4i64:
; X32-AVX1: # BB#0:
-; X32-AVX1-NEXT: vpextrd $1, %xmm1, %eax
-; X32-AVX1-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; X32-AVX1-NEXT: vpsrlq %xmm1, %xmm2, %xmm2
; X32-AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
@@ -572,8 +570,6 @@ define <4 x i64> @splatvar_shift_v4i64(<
;
; X32-AVX2-LABEL: splatvar_shift_v4i64:
; X32-AVX2: # BB#0:
-; X32-AVX2-NEXT: vpextrd $1, %xmm1, %eax
-; X32-AVX2-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X32-AVX2-NEXT: vpsrlq %xmm1, %ymm0, %ymm0
; X32-AVX2-NEXT: retl
%splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer
Modified: llvm/trunk/test/CodeGen/X86/vector-shift-shl-256.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shift-shl-256.ll?rev=308617&r1=308616&r2=308617&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-shift-shl-256.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-shift-shl-256.ll Thu Jul 20 06:48:17 2017
@@ -506,8 +506,6 @@ define <4 x i64> @splatvar_shift_v4i64(<
;
; X32-AVX1-LABEL: splatvar_shift_v4i64:
; X32-AVX1: # BB#0:
-; X32-AVX1-NEXT: vpextrd $1, %xmm1, %eax
-; X32-AVX1-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X32-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
; X32-AVX1-NEXT: vpsllq %xmm1, %xmm2, %xmm2
; X32-AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0
@@ -516,8 +514,6 @@ define <4 x i64> @splatvar_shift_v4i64(<
;
; X32-AVX2-LABEL: splatvar_shift_v4i64:
; X32-AVX2: # BB#0:
-; X32-AVX2-NEXT: vpextrd $1, %xmm1, %eax
-; X32-AVX2-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; X32-AVX2-NEXT: vpsllq %xmm1, %ymm0, %ymm0
; X32-AVX2-NEXT: retl
%splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer
Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.ll?rev=308617&r1=308616&r2=308617&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-512-v8.ll Thu Jul 20 06:48:17 2017
@@ -2735,8 +2735,6 @@ define <2 x i64> @test_v8i64_2_5 (<8 x i
; AVX512F-32-LABEL: test_v8i64_2_5:
; AVX512F-32: # BB#0:
; AVX512F-32-NEXT: vextracti32x4 $1, %zmm0, %xmm1
-; AVX512F-32-NEXT: vpextrd $1, %xmm1, %eax
-; AVX512F-32-NEXT: vpinsrd $1, %eax, %xmm1, %xmm1
; AVX512F-32-NEXT: vextracti32x4 $2, %zmm0, %xmm0
; AVX512F-32-NEXT: vpextrd $2, %xmm0, %eax
; AVX512F-32-NEXT: vpinsrd $2, %eax, %xmm1, %xmm1
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