[PATCH] D35647: [lld] [COFF] Support 128 bit SIMD/FP ldr/str in IMAGE_REL_ARM64_PAGEOFFSET_12L

[Martin Storsjö via Phabricator via llvm-commits]

mstorsjo added a comment.

In https://reviews.llvm.org/D35647#815648, @ruiu wrote:

> I wanted to ask about IMAGE_REL_ARM64_PAGEOFFSET_12L. Sorry for the confusion. The reason why I wanted more information is because, with this patch, a relocation with this relocation type behaves differently depending on an instruction to which the relocation is applied.  I think that is not common. Usually, relocations are agnostic on instructions they are modifying but just blindly mutate bits where they are applied. If you need some different behavior, I thought you'd define a different relocation type.
>
> That being said, is this behavior the same as the Microsoft linker? If so, it's correct whether it is odd or not.


Yes, I've checked it with their linker. (Even though the MSVC compiler for ARM64 isn't available publicly yet, link.exe from MSVC 2013 and onwards already seems to support ARM64.)

I think the sizes are separate relocation types in other object file types, but perhaps Microsoft wanted to save on the number of different relocation. (What's the available range for them in COFF?)



================
Comment at: COFF/Chunks.cpp:190
+  // the third bit in Size.
+  if (((Orig >> 26) & 1) != 0) // SIMD/FP
+    Size |= ((Orig >> 23) & 0x01) << 2;
----------------
mstorsjo wrote:
> ruiu wrote:
> > This is probably more straightforward:
> > 
> >   if (Orig & 0x280000)
> >     Size += 4;
> Sure - I'll update the patch later today.
Actually, it'd be like this:
```
// 0x04000000 indicates SIMD/FP registers
// 0x00800000 indicates 128 bit
if ((Orig & 0x4800000) == 0x4800000)
  Size += 4;
```



https://reviews.llvm.org/D35647