[llvm] r308542 - GlobalISel: partially revert r308540.

Tim Northover via llvm-commits llvm-commits at lists.llvm.org
Wed Jul 19 15:11:08 PDT 2017


Author: tnorthover
Date: Wed Jul 19 15:11:08 2017
New Revision: 308542

URL: http://llvm.org/viewvc/llvm-project?rev=308542&view=rev
Log:
GlobalISel: partially revert r308540.

An unfinished and untested implementation of ISel for G_UNMERGE_VALUES crept in
by mistake.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp?rev=308542&r1=308541&r2=308542&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstructionSelector.cpp Wed Jul 19 15:11:08 2017
@@ -780,30 +780,6 @@ bool AArch64InstructionSelector::select(
 
     return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
   }
-  case TargetOpcode::G_UNMERGE_VALUES: {
-    // 
-    LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
-    // Larger extracts are vectors, same-size extracts should be something else
-    // by now (either split up or simplified to a COPY).
-    if (SrcTy.getSizeInBits() > 64 || Ty.getSizeInBits() > 32)
-      return false;
-
-    I.setDesc(TII.get(AArch64::UBFMXri));
-    MachineInstrBuilder(MF, I).addImm(I.getOperand(2).getImm() +
-                                      Ty.getSizeInBits() - 1);
-
-    unsigned DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
-    BuildMI(MBB, std::next(I.getIterator()), I.getDebugLoc(),
-            TII.get(AArch64::COPY))
-        .addDef(I.getOperand(0).getReg())
-        .addUse(DstReg, 0, AArch64::sub_32);
-    RBI.constrainGenericRegister(I.getOperand(0).getReg(),
-                                 AArch64::GPR32RegClass, MRI);
-    I.getOperand(0).setReg(DstReg);
-
-    return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
-  }
-
   case TargetOpcode::G_INSERT: {
     LLT SrcTy = MRI.getType(I.getOperand(2).getReg());
     // Larger inserts are vectors, same-size ones should be something else by




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