[PATCH] D35058: [docs] Document how to debug instruction scheduling model generation

[Joel Jones via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL308476: [docs] Document how to debug instruction scheduling model generation (authored by joel_k_jones).

Changed prior to commit:
  https://reviews.llvm.org/D35058?vs=107129&id=107296#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D35058

Files:
  llvm/trunk/docs/WritingAnLLVMBackend.rst


Index: llvm/trunk/docs/WritingAnLLVMBackend.rst
===================================================================
--- llvm/trunk/docs/WritingAnLLVMBackend.rst
+++ llvm/trunk/docs/WritingAnLLVMBackend.rst
@@ -1012,6 +1012,46 @@
 by TableGen in XXXGenInstrInfo.inc. The name of the schedule classes are
 the same as provided in XXXSchedule.td plus a default NoItinerary class.
 
+The schedule models are generated by TableGen by the SubtargetEmitter,
+using the ``CodeGenSchedModels`` class. This is distinct from the itinerary
+method of specifying machine resource use.  The tool ``utils/schedcover.py``
+can be used to determine which instructions have been covered by the
+schedule model description and which haven't. The first step is to use the
+instructions below to create an output file. Then run ``schedcover.py`` on the
+output file:
+
+.. code-block:: shell
+
+  $ <src>/utils/schedcover.py <build>/lib/Target/AArch64/tblGenSubtarget.with
+  instruction, default, CortexA53Model, CortexA57Model, CycloneModel, ExynosM1Model, FalkorModel, KryoModel, ThunderX2T99Model, ThunderXT8XModel
+  ABSv16i8, WriteV, , , CyWriteV3, M1WriteNMISC1, FalkorWr_2VXVY_2cyc, KryoWrite_2cyc_XY_XY_150ln, , 
+  ABSv1i64, WriteV, , , CyWriteV3, M1WriteNMISC1, FalkorWr_1VXVY_2cyc, KryoWrite_2cyc_XY_noRSV_67ln, , 
+  ...
+
+To capture the debug output from generating a schedule model, change to the
+appropriate target directory and use the following command:
+command with the ``subtarget-emitter`` debug option:
+
+.. code-block:: shell
+
+  $ <build>/bin/llvm-tblgen -debug-only=subtarget-emitter -gen-subtarget \
+    -I <src>/lib/Target/<target> -I <src>/include \
+    -I <src>/lib/Target <src>/lib/Target/<target>/<target>.td \
+    -o <build>/lib/Target/<target>/<target>GenSubtargetInfo.inc.tmp \
+    > tblGenSubtarget.dbg 2>&1
+
+Where ``<build>`` is the build directory, ``src`` is the source directory,
+and ``<target>`` is the name of the target.
+To double check that the above command is what is needed, one can capture the
+exact TableGen command from a build by using:
+
+.. code-block:: shell
+
+  $ VERBOSE=1 make ... 
+
+and search for ``llvm-tblgen`` commands in the output.
+
+
 Instruction Relation Mapping
 ----------------------------
 


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