[PATCH] D35566: [DAG] Extend visitSCALAR_TO_VECTOR optimization to truncated vector.

[Nirav Dave via Phabricator via llvm-commits]

niravd created this revision.
Herald added a subscriber: javed.absar.

Allow SCALAR_TO_VECTOR of EXTRACT_VECTOR_ELT to reduce to
EXTRACT_SUBVECTOR of vector shuffle when output is smaller. Marginally
improves vector shuffle computations.


https://reviews.llvm.org/D35566

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/arm64-neon-copy.ll
  test/CodeGen/AArch64/neon-scalar-copy.ll


Index: test/CodeGen/AArch64/neon-scalar-copy.ll
===================================================================
--- test/CodeGen/AArch64/neon-scalar-copy.ll
+++ test/CodeGen/AArch64/neon-scalar-copy.ll
@@ -113,8 +113,7 @@
 
 define <1 x i32> @test_vector_dup_sv4S(<4 x i32> %v1) #0 {
  ; CHECK-LABEL: test_vector_dup_sv4S:
- ; CHECK-NEXT: mov  [[W:w[0-9]+]], v0.s[3]
- ; CHECK-NEXT: fmov s0, [[W]]
+ ; CHECK-NEXT: dup v0.4s, v0.s[3]
  ; CHECK-NEXT: ret
  %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <1 x i32> <i32 3> 
  ret <1 x i32> %shuffle
@@ -138,7 +137,7 @@
 
 define <1 x i64> @test_vector_copy_dup_dv2D(<1 x i64> %a, <2 x i64> %c) #0 {
   ; CHECK-LABEL: test_vector_copy_dup_dv2D:
-  ; CHECK-NEXT: {{dup|mov}} {{d[0-9]+}}, {{v[0-9]+}}.d[1]
+  ; CHECK-NEXT: dup v0.2d, v1.d[1]
   ; CHECK-NEXT: ret
   %vget_lane = extractelement <2 x i64> %c, i32 1
   %vset_lane = insertelement <1 x i64> undef, i64 %vget_lane, i32 0
Index: test/CodeGen/AArch64/arm64-neon-copy.ll
===================================================================
--- test/CodeGen/AArch64/arm64-neon-copy.ll
+++ test/CodeGen/AArch64/arm64-neon-copy.ll
@@ -188,7 +188,7 @@
 
 define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
 ; CHECK-LABEL: ins2f1:
-; CHECK: mov {{d[0-9]+}}, {{v[0-9]+}}.d[1]
+; CHECK: dup {{v[0-9]+}}.2d, {{v[0-9]+}}.d[1]
   %tmp3 = extractelement <2 x double> %tmp1, i32 1
   %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
   ret <1 x double> %tmp4
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -15622,19 +15622,27 @@
   if (InVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
     SDValue InVec = InVal->getOperand(0);
     SDValue EltNo = InVal->getOperand(1);
+    auto InVecT = InVec.getValueType();
 
-    // FIXME: We could support implicit truncation if the shuffle can be
-    // scaled to a smaller vector scalar type.
     ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(EltNo);
-    if (C0 && VT == InVec.getValueType() &&
-        VT.getScalarType() == InVal.getValueType()) {
-      SmallVector<int, 8> NewMask(VT.getVectorNumElements(), -1);
+    if (C0 && VT.getScalarType() == InVal.getValueType()) {
+      SmallVector<int, 8> NewMask(InVecT.getVectorNumElements(), -1);
       int Elt = C0->getZExtValue();
       NewMask[0] = Elt;
-
-      if (TLI.isShuffleMaskLegal(NewMask, VT))
+      if (VT == InVecT && TLI.isShuffleMaskLegal(NewMask, VT))
         return DAG.getVectorShuffle(VT, SDLoc(N), InVec, DAG.getUNDEF(VT),
                                     NewMask);
+      if (VT.getVectorNumElements() <= InVecT.getVectorNumElements() &&
+          TLI.isShuffleMaskLegal(NewMask, VT)) {
+        SDValue Shuff = DAG.getVectorShuffle(InVecT, SDLoc(N), InVec,
+                                             DAG.getUNDEF(InVecT), NewMask);
+        if (VT.getVectorNumElements() == InVecT.getVectorNumElements())
+          return Shuff;
+        MVT IdxTy = TLI.getVectorIdxTy(DAG.getDataLayout());
+        SDValue ZeroIdx = DAG.getConstant(0, SDLoc(N), IdxTy);
+        return DAG.getNode(ISD::EXTRACT_SUBVECTOR, SDLoc(N), VT, Shuff,
+                           ZeroIdx);
+      }
     }
   }
 


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