[PATCH] D35446: Add an ID field to StackObjects

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Jul 14 19:10:57 PDT 2017


arsenm created this revision.
Herald added subscribers: tpr, javed.absar, nhaehnle, wdng, qcolombet.

On AMDGPU SGPR spills are really spilled to another register.
The spiller creates the spills to new frame index objects,
which is used as a placeholder.

      

This will eventually be replaced with a reference to a position
in a VGPR to write to and the frame index deleted. It is
most likely not a real stack location that can be shared
with another stack object.

      

This is a problem when StackSlotColoring decides it should
combine a frame index used for a normal VGPR spill with
a real stack location and a frame index used for an SGPR.

      

Add an ID field so that StackSlotColoring has a way
of knowing the different frame index types are
incompatible.


https://reviews.llvm.org/D35446

Files:
  include/llvm/CodeGen/MIRYamlMapping.h
  include/llvm/CodeGen/MachineFrameInfo.h
  include/llvm/CodeGen/MachineMemOperand.h
  lib/CodeGen/MIRParser/MIRParser.cpp
  lib/CodeGen/MIRPrinter.cpp
  lib/CodeGen/MachineFrameInfo.cpp
  lib/CodeGen/MachineInstr.cpp
  lib/CodeGen/StackSlotColoring.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
  test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
  test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
  test/CodeGen/MIR/AMDGPU/stack-id.mir
  test/CodeGen/MIR/X86/callee-saved-info.mir
  test/CodeGen/MIR/X86/fixed-stack-objects.mir
  test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
  test/CodeGen/MIR/X86/stack-objects.mir
  test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
  test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll

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