[PATCH] D35058: [docs] Document how to debug instruction scheduling model generation

[Joel Jones via Phabricator via llvm-commits]

joelkevinjones updated this revision to Diff 106686.
joelkevinjones edited the summary of this revision.
joelkevinjones added a comment.

Describe distinction between sched model and itinerary vis-a-vis schedcover.py.
Give complete command for llvm-tblgen debug output


Repository:
  rL LLVM

https://reviews.llvm.org/D35058

Files:
  docs/WritingAnLLVMBackend.rst


Index: docs/WritingAnLLVMBackend.rst
===================================================================
--- docs/WritingAnLLVMBackend.rst
+++ docs/WritingAnLLVMBackend.rst
@@ -1012,6 +1012,46 @@
 by TableGen in XXXGenInstrInfo.inc. The name of the schedule classes are
 the same as provided in XXXSchedule.td plus a default NoItinerary class.
 
+The schedule models are generated by TableGen by the SubtargetEmitter,
+using the ``CodeGenSchedModels`` class. This is distinct from the itinerary
+method of specifying machine resource use.  The tool ``utils/schedcover.py``
+can be used to determine which instructions have been covered by the
+schedule model description and which haven't. The first step is to use the
+instructions below to create an output file. Then run ``schedcover.py`` on the
+output file:
+
+.. code-block:: shell
+
+  $ utils/schedcover.py build/lib/Target/AArch64/tblGenSubtarget.with
+  instruction, default, CortexA53Model, CortexA57Model, CycloneModel, ExynosM1Model, FalkorModel, KryoModel, ThunderX2T99Model, ThunderXT8XModel
+  ABSv16i8, WriteV, , , CyWriteV3, M1WriteNMISC1, FalkorWr_2VXVY_2cyc, KryoWrite_2cyc_XY_XY_150ln, , 
+  ABSv1i64, WriteV, , , CyWriteV3, M1WriteNMISC1, FalkorWr_1VXVY_2cyc, KryoWrite_2cyc_XY_noRSV_67ln, , 
+  ...
+
+To capture the debug output from generating a schedule model, change to the
+appropriate target directory and use the following command:
+command with the ``subtarget-emitter`` debug option:
+
+.. code-block:: shell
+
+  $ <build>/bin/llvm-tblgen -debug-only=subtarget-emitter -gen-subtarget \
+    -I <build>/../lib/Target/AArch64 -I <build>/../include \
+    -I <build>/../lib/Target <build>/../lib/Target/<target>/<target>.td \
+    -o <build>/lib/Target/<target>/<target>GenSubtargetInfo.inc.tmp \
+    > tblGenSubtarget.dbg 2>&1
+
+Where ``<build>`` is the build directory and ``<target>`` is the name of the
+target.
+To double check that the above command is what is needed, one can capture the
+exact TableGen command from a build by using:
+
+.. code-block:: shell
+
+  $ VERBOSE=1 make ... 
+
+and search for ``llvm-tblgen`` commands in the output.
+
+
 Instruction Relation Mapping
 ----------------------------
 


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D35058.106686.patch
Type: text/x-patch
Size: 2200 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170714/38160aef/attachment.bin>