[llvm] r307937 - [X86][tests] Added rotate_vec.ll CodeGen test. NFC precommit for bug 33691 fix.

[Andrew Zhogin via llvm-commits]

Author: andrew.zhogin
Date: Thu Jul 13 11:57:40 2017
New Revision: 307937

URL: http://llvm.org/viewvc/llvm-project?rev=307937&view=rev
Log:
[X86][tests] Added rotate_vec.ll CodeGen test. NFC precommit for bug 33691 fix.

Added:
    llvm/trunk/test/CodeGen/X86/rotate_vec.ll

Added: llvm/trunk/test/CodeGen/X86/rotate_vec.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/rotate_vec.ll?rev=307937&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/rotate_vec.ll (added)
+++ llvm/trunk/test/CodeGen/X86/rotate_vec.ll Thu Jul 13 11:57:40 2017
@@ -0,0 +1,60 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=bdver4 | FileCheck %s
+
+define <4 x i32> @rot_v4i32_splat(<4 x i32> %x) {
+; CHECK-LABEL: rot_v4i32_splat:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vprotd $31, %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
+  %2 = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+  %3 = or <4 x i32> %1, %2
+  ret <4 x i32> %3
+}
+
+define <4 x i32> @rot_v4i32_non_splat(<4 x i32> %x) {
+; CHECK-LABEL: rot_v4i32_non_splat:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT:    vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    vpor %xmm0, %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>
+  %2 = shl <4 x i32> %x, <i32 31, i32 30, i32 29, i32 28>
+  %3 = or <4 x i32> %1, %2
+  ret <4 x i32> %3
+}
+
+define <4 x i32> @rot_v4i32_splat_2masks(<4 x i32> %x) {
+; CHECK-LABEL: rot_v4i32_splat_2masks:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vprotd $31, %xmm0, %xmm0
+; CHECK-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    retq
+  %1 = lshr <4 x i32> %x, <i32 1, i32 1, i32 1, i32 1>
+  %2 = and <4 x i32> %1, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
+
+  %3 = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
+  %4 = and <4 x i32> %3, <i32 0, i32 4294901760, i32 0, i32 4294901760>
+  %5 = or <4 x i32> %2, %4
+  ret <4 x i32> %5
+}
+
+define <4 x i32> @rot_v4i32_non_splat_2masks(<4 x i32> %x) {
+; CHECK-LABEL: rot_v4i32_non_splat_2masks:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    vpsrlvd {{.*}}(%rip), %xmm0, %xmm1
+; CHECK-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; CHECK-NEXT:    vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3],xmm2[4],xmm1[5],xmm2[6],xmm1[7]
+; CHECK-NEXT:    vpsllvd {{.*}}(%rip), %xmm0, %xmm0
+; CHECK-NEXT:    vpblendw {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[3],xmm2[4,5,6],xmm0[7]
+; CHECK-NEXT:    vpor %xmm0, %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 3, i32 4>
+  %2 = and <4 x i32> %1, <i32 4294901760, i32 4294901760, i32 4294901760, i32 4294901760>
+
+  %3 = shl <4 x i32> %x, <i32 31, i32 30, i32 29, i32 28>
+  %4 = and <4 x i32> %3, <i32 0, i32 4294901760, i32 0, i32 4294901760>
+  %5 = or <4 x i32> %2, %4
+  ret <4 x i32> %5
+}