[PATCH] D35307: [AArch64] Initial SVE register definitions

[Amara Emerson via Phabricator via llvm-commits]

aemerson added a comment.

In https://reviews.llvm.org/D35307#806713, @rengolin wrote:

> Hi Amara,
>
> This seems a very raw change, without any further description, comments or proper usage, other than a few changes on random places.


I don't agree. The additions are in line with the level of documentation in the rest of the file. This is essentially an NFC change until we begin to add support for the actual instructions. To do so, first we need some minimal registers and regclasses defined.

> You have to describe what the changes are meant to do, where the documents are (as a refresher), which chapters of the documents those registers are described, and hopefully some use of them somewhere.

The architecture reference manual supplement describes SVE in more detail: https://developer.arm.com/docs/ddi0584/latest/arm-architecture-reference-manual-supplement-the-scalable-vector-extension-sve-for-armv8-a
We do not have a full release of the ARMARM to reference yet.

> Is it not possible to write tests for them? If so, why not?

Unless the registers are used in an instruction, I'm not aware of any way to test them. Happy to do so if you have a suggestion on this though.

> Is this the first of a series? If yes, there what's the rest? A description of the changes would help, but much better if you pointer to more reviews in the series.

Not really, the rest of the patches will come eventually but we're waiting on foundations and infrastructure to committed first before we prepare next steps. We're trying to break down the entire SVE support into small pieces.


Repository:
  rL LLVM

https://reviews.llvm.org/D35307