[PATCH] D35299: [AArch64] Tie source and destination operands for AESMC/AESIMC.

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

In https://reviews.llvm.org/D35299#807213, @evandro wrote:

> In https://reviews.llvm.org/D35299#807127, @fhahn wrote:
>
> > But unless Vk == Vi for AESMC/AESIMC, the most CPUs won't be able to fuse the pair and  won't execute it more efficiently.
>
>
> Perhaps most CPUs require this, but certainly not all.  Thus, would there be a way to make this constraint specific to such CPUs?


One solution I could think of would be to add pseudo AESMC/AESIMC instructions and expand them to either AESMC/AESIMC with constraint or without constraint, depending on the target-features. There probably is a more elegant solution I am not aware of though, so I would appreciate any input :)


https://reviews.llvm.org/D35299