[PATCH] D35007: [PowerPC] Do not emit displacements for DQ-Form instructions that aren't multiples of 16

[Hal Finkel via Phabricator via llvm-commits]

hfinkel added a comment.

> Although the instruction doesn't require any special alignment, allowing it to be used with weaker alignment allows other passes to modify the offset after ISEL.

For what other passes is this true (aside from places dealing with frame indices, which it seems like you're fixing regardless)?



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Comment at: lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp:274
   const MCOperand &MO = MI.getOperand(OpNo);
-  assert(MO.isImm());
+  assert(MO.isImm() && !(MO.getImm() % 16) &&
+         "Expecting an immediate that is a multiple of 16");
----------------
If you use the builtin assembler directly, can a user hit this assert? If so, we should put an actual diagnostic somewhere.


Repository:
  rL LLVM

https://reviews.llvm.org/D35007