[llvm] r307653 - [ARM] GlobalISel: Add reg mapping for s64 G_FCMP

[Diana Picus via llvm-commits]

Author: rovka
Date: Tue Jul 11 04:47:45 2017
New Revision: 307653

URL: http://llvm.org/viewvc/llvm-project?rev=307653&view=rev
Log:
[ARM] GlobalISel: Add reg mapping for s64 G_FCMP

Map the result into GPR and the operands into FPR.

Modified:
    llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
    llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=307653&r1=307652&r2=307653&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Tue Jul 11 04:47:45 2017
@@ -279,16 +279,20 @@ ARMRegisterBankInfo::getInstrMapping(con
   }
   case G_FCMP: {
     LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
-    (void)Ty1;
     LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
     (void)Ty2;
     assert(Ty.getSizeInBits() == 1 && "Unsupported size for G_FCMP");
-    assert(Ty1.getSizeInBits() == 32 && "Unsupported size for G_FCMP");
-    assert(Ty2.getSizeInBits() == 32 && "Unsupported size for G_FCMP");
+    assert(Ty1.getSizeInBits() == Ty2.getSizeInBits() &&
+           "Mismatched operand sizes for G_FCMP");
+
+    unsigned Size = Ty1.getSizeInBits();
+    assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP");
+
+    auto FPRValueMapping = Size == 32 ? &ARM::ValueMappings[ARM::SPR3OpsIdx]
+                                      : &ARM::ValueMappings[ARM::DPR3OpsIdx];
     OperandsMapping =
         getOperandsMapping({&ARM::ValueMappings[ARM::GPR3OpsIdx], nullptr,
-                            &ARM::ValueMappings[ARM::SPR3OpsIdx],
-                            &ARM::ValueMappings[ARM::SPR3OpsIdx]});
+                            FPRValueMapping, FPRValueMapping});
     break;
   }
   case G_MERGE_VALUES: {

Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=307653&r1=307652&r2=307653&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Tue Jul 11 04:47:45 2017
@@ -36,6 +36,7 @@
 
   define void @test_icmp_eq_s32() { ret void }
   define void @test_fcmp_one_s32() #0 { ret void }
+  define void @test_fcmp_ugt_s64() #0 { ret void }
 
   define void @test_select_s32() { ret void }
 
@@ -769,6 +770,34 @@ body:             |
     %3(s32) = G_ZEXT %2(s1)
     %r0 = COPY %3(s32)
     BX_RET 14, _, implicit %r0
+
+...
+---
+name:            test_fcmp_ugt_s64
+# CHECK-LABEL: name: test_fcmp_ugt_s64
+legalized:       true
+regBankSelected: false
+selected:        false
+# CHECK: registers:
+# CHECK: - { id: 0, class: fprb, preferred-register: '' }
+# CHECK: - { id: 1, class: fprb, preferred-register: '' }
+# CHECK: - { id: 2, class: gprb, preferred-register: '' }
+
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+  - { id: 3, class: _ }
+body:             |
+  bb.0:
+    liveins: %d0, %d1
+
+    %0(s64) = COPY %d0
+    %1(s64) = COPY %d1
+    %2(s1) = G_FCMP floatpred(ugt), %0(s64), %1
+    %3(s32) = G_ZEXT %2(s1)
+    %r0 = COPY %3(s32)
+    BX_RET 14, _, implicit %r0
 
 ...
 ---