[llvm] r307640 - [ARM] ldr pc, =expression should be allowed in Thumb2

[Peter Smith via llvm-commits]

Author: psmith
Date: Tue Jul 11 02:47:12 2017
New Revision: 307640

URL: http://llvm.org/viewvc/llvm-project?rev=307640&view=rev
Log:
[ARM] ldr pc,=expression should be allowed in Thumb2

This change allows the pc to be used as a destination register for the
pseudo instruction LDR pc,=expression . The pseudo instruction must not be
transformed into a MOV, but it can use the Thumb2 LDR (literal) instruction
to a constant pool entry. See (A7.7.43 from ARMv7M ARM ARM).

Differential Revision: https://reviews.llvm.org/D34751


Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/MC/ARM/ldr-pseudo-unpredictable.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=307640&r1=307639&r2=307640&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jul 11 02:47:12 2017
@@ -4799,7 +4799,7 @@ def : t2InstAlias<"add${p} $Rd, pc, $imm
 // Pseudo instruction ldr Rt, =immediate
 def t2LDRConstPool
   : t2AsmPseudo<"ldr${p} $Rt, $immediate",
-                (ins GPRnopc:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;
+                (ins GPR:$Rt, const_pool_asm_imm:$immediate, pred:$p)>;
 // Version w/ the .w suffix.
 def : t2InstAlias<"ldr${p}.w $Rt, $immediate",
                   (t2LDRConstPool GPRnopc:$Rt,

Modified: llvm/trunk/test/MC/ARM/ldr-pseudo-unpredictable.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/ldr-pseudo-unpredictable.s?rev=307640&r1=307639&r2=307640&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/ldr-pseudo-unpredictable.s (original)
+++ llvm/trunk/test/MC/ARM/ldr-pseudo-unpredictable.s Tue Jul 11 02:47:12 2017
@@ -1,8 +1,8 @@
 @RUN: llvm-mc -triple armv5-unknown-linux-gnueabi %s | FileCheck --check-prefix=CHECK-ARM %s
- at RUN: not llvm-mc -triple thumbv7-unknown-linux-gnueabi %s 2>&1 | FileCheck --check-prefix=CHECK-SP %s
+ at RUN: llvm-mc -triple thumbv7-unknown-linux-gnueabi %s 2>&1 | FileCheck --check-prefix=CHECK-T2 %s
 @RUN: not llvm-mc -triple thumbv5-unknown-linux-gnueabi %s 2>&1 | FileCheck --check-prefix=CHECK-NONE %s
 @RUN: llvm-mc -triple armv5-base-apple-darwin %s | FileCheck --check-prefix=CHECK-DARWIN-ARM %s
- at RUN: not llvm-mc -triple thumbv7-base-apple-darwin %s 2>&1 | FileCheck --check-prefix=CHECK-DARWIN-SP %s
+ at RUN: llvm-mc -triple thumbv7-base-apple-darwin %s 2>&1 | FileCheck --check-prefix=CHECK-DARWIN-T2 %s
 @RUN: not llvm-mc -triple thumbv5-base.apple.darwin %s 2>&1 | FileCheck --check-prefix=CHECK-NONE %s
 
 @ We dont't do the transformation for rt = sp or pc
@@ -10,12 +10,12 @@
   ldr pc, = 0x4
 @ CHECK-ARM: ldr pc, .Ltmp[[TMP0:[0-9]+]]
 @ CHECK-DARWIN-ARM: ldr pc, Ltmp0
-@ CHECK-SP: error: instruction requires: arm-mode
-@ CHECK-DARWIN-SP: error: instruction requires: arm-mode
-@ CHECK-NONE: error: instruction requires: arm-mode
+@ CHECK-T2: ldr.w pc, .Ltmp[[TMP0:[0-9]+]]
+@ CHECK-DARWIN-T2: ldr.w pc, Ltmp0
+@ CHECK-NONE: error: instruction requires: thumb2
   ldr sp, = 0x8
 @ CHECK-ARM: ldr sp, .Ltmp[[TMP1:[0-9]+]]
 @ CHECK-DARWIN-ARM: ldr sp, Ltmp1
-@ CHECK-SP: ldr.w sp, .Ltmp[[TMP0:[0-9]+]]
-@ CHECK-DARWIN-SP: ldr.w sp, Ltmp0
-@ CHECK-NONE: error: instruction requires: arm-mode
+@ CHECK-T2: ldr.w sp, .Ltmp[[TMP1:[0-9]+]]
+@ CHECK-DARWIN-T2: ldr.w sp, Ltmp1
+@ CHECK-NONE: error: instruction requires: thumb2