[PATCH] D35007: [PowerPC] Do not emit displacements for DQ-Form instructions that aren't multiples of 16

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai updated this revision to Diff 105651.
nemanjai added a comment.

As it turns out, I was wrong in my assessment of Hal's comment. Although the instruction doesn't require any special alignment, allowing it to be used with weaker alignment allows other passes to modify the offset after ISEL. So the fact that we verify that `Offset % 16` during ISEL isn't sufficient.
Furthermore, when we eliminate the `FrameIndex` the code does not have any awareness of instructions that need an immediate that is a multiple of 16.
I've made the following updates:

- Don't emit `LXV/STXV` for unaligned loads/stores (use the X-Forms for that)
- Teach FI elimination that some instructions need immediates that are multiples of 16
- Fix the test cases that changed behaviour
- Assert if we somehow end up with an instruction that needs an immediate as multiple of 16 but has an incorrect immediate
- Specify alignment to the function that generates the displacements during ISEL
- Add missing DS-Form instructions to the list of instructions that need a multiple-of-4 immediate
- Fix loads/stores that were using incorrect addressing
- Divide up the loads/stores into those that can handle unaligned addresses and those that can't


Repository:
  rL LLVM

https://reviews.llvm.org/D35007

Files:
  lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
  lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  lib/Target/PowerPC/PPCISelLowering.cpp
  lib/Target/PowerPC/PPCISelLowering.h
  lib/Target/PowerPC/PPCInstrAltivec.td
  lib/Target/PowerPC/PPCInstrInfo.td
  lib/Target/PowerPC/PPCInstrVSX.td
  lib/Target/PowerPC/PPCRegisterInfo.cpp
  test/CodeGen/PowerPC/PR33671.ll
  test/CodeGen/PowerPC/build-vector-tests.ll

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