[PATCH] D35127: AMDGPU/GlobalISel: Mark 32-bit G_OR as legal
Tom Stellard via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 7 09:25:37 PDT 2017
tstellar created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, igorb, kristof.beyls, rovka, yaxunl, nhaehnle, wdng, kzhuravl.
https://reviews.llvm.org/D35127
Files:
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
Index: test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir
@@ -0,0 +1,21 @@
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+--- |
+ define void @test_or() { ret void }
+...
+---
+name: test_or
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+ - { id: 2, class: _ }
+body: |
+ bb.0:
+ liveins: %vgpr0, %vgpr1
+ ; CHECK-LABEL: name: test_or
+ ; CHECK: %2(s32) = G_OR %0, %1
+
+ %0(s32) = COPY %vgpr0
+ %1(s32) = COPY %vgpr1
+ %2(s32) = G_OR %0, %1
+...
Index: lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -66,6 +66,8 @@
setAction({G_LOAD, 1, P1}, Legal);
setAction({G_LOAD, 1, P2}, Legal);
+ setAction({G_OR, S32}, Legal);
+
setAction({G_SELECT, S32}, Legal);
setAction({G_SELECT, 1, S1}, Legal);
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