[PATCH] D34569: [DAGCombine] Improve Store Merge logic to merge bitcast extracts.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12523
+                            : Other->getMemoryVT() != MemVT)
+        return false;
       // The Load's Base Ptr must also match
----------------
It'd probably be better if you avoid the ternary inside the if().
```
if (MemVT.isInteger() && !MemVT.bitsEq(Other->getMemoryVT()))
   return false;
if (!MemVT.isInteger() && Other->getMemoryVT() != MemVT)
   return false;
```
or
```
if ((MemVT.isInteger() && !MemVT.bitsEq(Other->getMemoryVT())) ||
    (!MemVT.isInteger() && Other->getMemoryVT() != MemVT))
   return false;
```
That or pull it out as a bool variable in the line above.


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:12536
+                            : Other->getMemoryVT() != MemVT)
+        return false;
       if (!(isa<ConstantSDNode>(Other->getValue()) ||
----------------
Another ternary inside an if()


https://reviews.llvm.org/D34569