[PATCH] D34961: [AArch64] Use 16 bytes as preferred function alignment on Cortex-A72.

Chad Rosier via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jul 6 10:17:29 PDT 2017

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mcrosier resigned from this revision.
mcrosier added a comment.

>From a coding standpoint this all LGTM.  However, I'm going to defer to a A72 code owner for final approval.


https://reviews.llvm.org/D34961

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