[PATCH] D35007: [PowerPC] Do not emit displacements for DQ-Form instructions that aren't multiples of 16

[Hal Finkel via Phabricator via llvm-commits]

hfinkel added inline comments.


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Comment at: lib/Target/PowerPC/PPCInstrInfo.td:408
+// instructions).
+def aligned16load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
+  return isOffsetMultipleOf(N, 16);
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nemanjai wrote:
> If this solution is the way we want to proceed, perhaps it would be good to use the same approach for DS-Form instructions. These ultimately don't need to be aligned, they just can't have a displacement that isn't a multiple of 4.
Why can't we just check `cast<LoadSDNode>(N)->getAlignment() >= 16;` like we do above?


Repository:
  rL LLVM

https://reviews.llvm.org/D35007