[PATCH] D35011: [ARM] add v4f16 and v8f16 as legal types

[Sjoerd Meijer via Phabricator via llvm-commits]

SjoerdMeijer created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

This is addressing an issue exposed by commit https://reviews.llvm.org/rL305820, see also https://reviews.llvm.org/D34161, which adds the ARMv.2-A FP16 vector intrinsics.
Due to this patch the backend now gets <4 x half> and <8 x half>types which wasn't the case before, and it doesn't know how to deal with them.

I am sharing my work in progress here when I learned that Samsung is also working on a solution; perhaps this helps and/or thus we can speed things up.

Essentially, the approach taken here is to add types MVT::v4f16 and MVT::v8f16 only when ##hasFullFP16## is enabled; this makes sure we don't change the old behaviour.
All regression tests pass with this patch, except the last one of a series of new tests that I added: i.e. a function that accepts and returns a <8 x half> type, see function ##variable_insertelement## in ##vstlane-v8.ll##. I am still working on fixing this.

Please let me know what you think, if you have ideas, or e.g. have taken another approach.


https://reviews.llvm.org/D35011

Files:
  lib/Target/ARM/ARMCallingConv.td
  lib/Target/ARM/ARMISelDAGToDAG.cpp
  lib/Target/ARM/ARMISelLowering.cpp
  lib/Target/ARM/ARMInstrNEON.td
  test/CodeGen/ARM/vstlane-v4.ll
  test/CodeGen/ARM/vstlane-v8.ll

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