[PATCH] D34869: [PowerPC] fix latency for simple integer instructions in POWER9 scheduler

[Hiroshi Inoue via Phabricator via llvm-commits]

inouehrs created this revision.

In the POWER9 instruction scheduler, SchedWriteRes for the simple integer instructions are misconfigured to use that of (costly) DFU instructions.
This results in surprisingly long instruction latency estimation and causes misbehavior in some optimizers such as if-conversion.


https://reviews.llvm.org/D34869

Files:
  lib/Target/PowerPC/PPCScheduleP9.td


Index: lib/Target/PowerPC/PPCScheduleP9.td
===================================================================
--- lib/Target/PowerPC/PPCScheduleP9.td
+++ lib/Target/PowerPC/PPCScheduleP9.td
@@ -260,7 +260,7 @@
 
   // ***************** Defining Itinerary Class Resources *****************
 
-  def : ItinRW<[P9_DFU_76C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntSimple,
+  def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C], [IIC_IntSimple,
                                          IIC_IntGeneral]>;
 
   def : ItinRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],


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