[PATCH] D34857: [COFF, ARM64] Add initial relocation types for COFF ARM64 target

[Mandeep Singh Grang via Phabricator via llvm-commits]

mgrang created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

Repository:
  rL LLVM

https://reviews.llvm.org/D34857

Files:
  lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp
  test/MC/AArch64/coff-relocations.s


Index: test/MC/AArch64/coff-relocations.s
===================================================================
--- /dev/null
+++ test/MC/AArch64/coff-relocations.s
@@ -0,0 +1,16 @@
+; RUN: llvm-mc -triple aarch64-windows -filetype obj -o - %s \
+; RUN:   | llvm-readobj -r - | FileCheck %s -check-prefix CHECK-RELOC
+
+branch26:
+  b target
+
+pagebase_rel21:
+  adrp x0, foo
+
+
+; CHECK-RELOC: Relocations [
+; CHECK-RELOC:   Section (1) .text {
+; CHECK-RELOC:     0x0 IMAGE_REL_ARM64_BRANCH26 target
+; CHECK-RELOC:     0x4 IMAGE_REL_ARM64_PAGEBASE_REL21 foo
+; CHECK-RELOC:   }
+; CHECK-RELOC: ]
Index: lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp
+++ lib/Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp
@@ -47,8 +47,31 @@
                                          const MCFixup &Fixup,
                                          bool IsCrossSection,
                                          const MCAsmBackend &MAB) const {
-  const MCFixupKindInfo &Info = MAB.getFixupKindInfo(Fixup.getKind());
-  report_fatal_error(Twine("unsupported relocation type: ") + Info.Name);
+  switch (static_cast<unsigned>(Fixup.getKind())) {
+  default: {
+    const MCFixupKindInfo &Info = MAB.getFixupKindInfo(Fixup.getKind());
+    report_fatal_error(Twine("unsupported relocation type: ") + Info.Name);
+  }
+  case FK_Data_8:
+    return COFF::IMAGE_REL_ARM64_ADDR64;
+
+  case AArch64::fixup_aarch64_add_imm12:
+   return COFF::IMAGE_REL_ARM64_PAGEOFFSET_12A;
+
+  case AArch64::fixup_aarch64_ldst_imm12_scale1:
+  case AArch64::fixup_aarch64_ldst_imm12_scale2:
+  case AArch64::fixup_aarch64_ldst_imm12_scale4:
+  case AArch64::fixup_aarch64_ldst_imm12_scale8:
+  case AArch64::fixup_aarch64_ldst_imm12_scale16:
+   return COFF::IMAGE_REL_ARM64_PAGEOFFSET_12L;
+
+  case AArch64::fixup_aarch64_pcrel_adrp_imm21:
+   return COFF::IMAGE_REL_ARM64_PAGEBASE_REL21;
+
+  case AArch64::fixup_aarch64_pcrel_branch26:
+  case AArch64::fixup_aarch64_pcrel_call26:
+   return COFF::IMAGE_REL_ARM64_BRANCH26;
+  }
 }
 
 bool AArch64WinCOFFObjectWriter::recordRelocation(const MCFixup &Fixup) const {


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