[PATCH] D34849: [AMDGPU] Add missing hazard for DPP-after-EXEC-write

Connor Abbott via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 29 17:00:25 PDT 2017


cwabbott created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.

Following the docs, we need at least 5 wait states between an EXEC write
and an instruction that uses DPP.


https://reviews.llvm.org/D34849

Files:
  lib/Target/AMDGPU/GCNHazardRecognizer.cpp


Index: lib/Target/AMDGPU/GCNHazardRecognizer.cpp
===================================================================
--- lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+++ lib/Target/AMDGPU/GCNHazardRecognizer.cpp
@@ -368,8 +368,9 @@
 int GCNHazardRecognizer::checkDPPHazards(MachineInstr *DPP) {
   const SIRegisterInfo *TRI = ST.getRegisterInfo();
 
-  // Check for DPP VGPR read after VALU VGPR write.
+  // Check for DPP VGPR read after VALU VGPR write and EXEC write.
   int DppVgprWaitStates = 2;
+  int DppExecWaitStates = 5;
   int WaitStatesNeeded = 0;
 
   for (const MachineOperand &Use : DPP->uses()) {
@@ -380,6 +381,10 @@
     WaitStatesNeeded = std::max(WaitStatesNeeded, WaitStatesNeededForUse);
   }
 
+  WaitStatesNeeded =
+      std::max(WaitStatesNeeded,
+               DppExecWaitStates - getWaitStatesSinceDef(AMDGPU::EXEC));
+
   return WaitStatesNeeded;
 }
 


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