[PATCH] D34847: [AMDGPU] Mark all export instructions as DisableWQM

[Connor Abbott via Phabricator via llvm-commits]

cwabbott created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.

Export instructions read from EXEC to determine what data to write if
the VM bit is on. If we inadvertently left WQM (or in the future, WWM)
on, we'd write pixels that we weren't supposed to.


https://reviews.llvm.org/D34847

Files:
  lib/Target/AMDGPU/SIInstrInfo.td
  test/CodeGen/AMDGPU/wqm.ll


Index: test/CodeGen/AMDGPU/wqm.ll
===================================================================
--- test/CodeGen/AMDGPU/wqm.ll
+++ test/CodeGen/AMDGPU/wqm.ll
@@ -12,24 +12,29 @@
   ret <4 x float> %tex
 }
 
-; Check that WQM is triggered by image samples and left untouched for loads...
+; Check that WQM is triggered by image samples and left untouched for loads,
+; but disabled for exports...
 ;
 ;CHECK-LABEL: {{^}}test2:
 ;CHECK-NEXT: ; %main_body
-;CHECK-NEXT: s_wqm_b64 exec, exec
+;CHECK: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
+;CHECK: s_wqm_b64 exec, exec
+;CHECK-SI: buffer_load_dword
+;CHECK-VI: flat_load_dword
+;CHECK: s_and_b64 exec, exec, [[ORIG]]
 ;CHECK-NOT: exec
-define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x float> %c) {
+;CHECK: exp
+define amdgpu_ps void @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr) {
 main_body:
+  %data = load float, float addrspace(1)* %ptr
+  %c = insertelement <4 x float> zeroinitializer, float %data, i32 0
   %c.1 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v4f32.v8i32(<4 x float> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #0
-  %c.2 = bitcast <4 x float> %c.1 to <4 x i32>
-  %c.3 = extractelement <4 x i32> %c.2, i32 0
-  %gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.3
-  %data = load float, float addrspace(1)* %gep
-  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %data, float undef, float undef, float undef, i1 true, i1 true) #1
+  %c.2 = extractelement <4 x float> %c.1, i32 0
+  call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %c.2, float undef, float undef, float undef, i1 true, i1 true) #1
   ret void
 }
 
-; ... but disabled for stores (and, in this simple case, not re-enabled).
+; ... and for stores (and, in this simple case, not re-enabled).
 ;
 ;CHECK-LABEL: {{^}}test3:
 ;CHECK-NEXT: ; %main_body
Index: lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.td
+++ lib/Target/AMDGPU/SIInstrInfo.td
@@ -817,6 +817,7 @@
   [(node (i8 timm:$tgt), (i8 timm:$en),
          f32:$src0, f32:$src1, f32:$src2, f32:$src3,
          (i1 timm:$compr), (i1 timm:$vm))]> {
+  let DisableWQM = 1;
   let AsmMatchConverter = "cvtExp";
 }
 


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