[PATCH] D34813: [llvm-objdump] Handle invalid instruction gracefully on ARM

[Eugene Leviant via Phabricator via llvm-commits]

evgeny777 created this revision.
Herald added subscribers: kristof.beyls, javed.absar, aemerson.

I have several stripped ARM binaries, which can't be correctly disassembled by llvm-objdump, because they intermix code with data. For instance compiling and disassembling this file:

  .text
    b l0
    .inst 0xffffffff
  l0:

results in this output:

  $a.0:
         0:	00 00 00 ea 	b	#0 <l0>
         4:	ff  <unknown>
         5:	ff ff ff 00 	ldrshteq	pc, [pc], #255

and after applying this patch the result is the same as GNU objdump has:

  $a.0:
         0:	00 00 00 ea 	b	#0 <l0>
         4:	ff ff ff ff  <unknown>

This happens because ARMDisasembler returns zero size when it fails to parse an instruction. On the contrary AArch64Disassembler always returns 4, so aarch64 binaries are disassembled correctly.


Repository:
  rL LLVM

https://reviews.llvm.org/D34813

Files:
  lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  test/tools/llvm-objdump/ARM/invalid-instruction.s


Index: test/tools/llvm-objdump/ARM/invalid-instruction.s
===================================================================
--- test/tools/llvm-objdump/ARM/invalid-instruction.s
+++ test/tools/llvm-objdump/ARM/invalid-instruction.s
@@ -0,0 +1,9 @@
+ at RUN: llvm-mc -triple arm-unknown-linux -filetype=obj %s | llvm-objdump -d - | FileCheck %s
+
+.text
+  b l0
+  .inst 0xffffffff
+l0:
+
+ at CHECK:            0: 00 00 00 ea   b #0 <l0>
+ at CHECK-NEXT:       4: ff ff ff ff  <unknown>
Index: lib/Target/ARM/Disassembler/ARMDisassembler.cpp
===================================================================
--- lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -486,7 +486,7 @@
     }
   }
 
-  Size = 0;
+  Size = 4;
   return MCDisassembler::Fail;
 }
 


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