[llvm] r306544 - [globalisel][tablegen] Multiple 80-col corrections.
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 28 06:50:04 PDT 2017
Author: dsanders
Date: Wed Jun 28 06:50:04 2017
New Revision: 306544
URL: http://llvm.org/viewvc/llvm-project?rev=306544&view=rev
Log:
[globalisel][tablegen] Multiple 80-col corrections.
Modified:
llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp
Modified: llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp?rev=306544&r1=306543&r2=306544&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp Wed Jun 28 06:50:04 2017
@@ -80,8 +80,8 @@ public:
return;
}
if (Ty.isVector()) {
- OS << "LLT::vector(" << Ty.getNumElements() << ", " << Ty.getScalarSizeInBits()
- << ")";
+ OS << "LLT::vector(" << Ty.getNumElements() << ", "
+ << Ty.getScalarSizeInBits() << ")";
return;
}
llvm_unreachable("Unhandled LLT");
@@ -96,7 +96,8 @@ class InstructionMatcher;
static Optional<LLTCodeGen> MVTToLLT(MVT::SimpleValueType SVT) {
MVT VT(SVT);
if (VT.isVector() && VT.getVectorNumElements() != 1)
- return LLTCodeGen(LLT::vector(VT.getVectorNumElements(), VT.getScalarSizeInBits()));
+ return LLTCodeGen(
+ LLT::vector(VT.getVectorNumElements(), VT.getScalarSizeInBits()));
if (VT.isInteger() || VT.isFloatingPoint())
return LLTCodeGen(LLT::scalar(VT.getSizeInBits()));
return None;
@@ -241,12 +242,18 @@ public:
return *static_cast<Kind *>(Predicates.back().get());
}
- typename PredicateVec::const_iterator predicates_begin() const { return Predicates.begin(); }
- typename PredicateVec::const_iterator predicates_end() const { return Predicates.end(); }
+ typename PredicateVec::const_iterator predicates_begin() const {
+ return Predicates.begin();
+ }
+ typename PredicateVec::const_iterator predicates_end() const {
+ return Predicates.end();
+ }
iterator_range<typename PredicateVec::const_iterator> predicates() const {
return make_range(predicates_begin(), predicates_end());
}
- typename PredicateVec::size_type predicates_size() const { return Predicates.size(); }
+ typename PredicateVec::size_type predicates_size() const {
+ return Predicates.size();
+ }
/// Emit a C++ expression that tests whether all the predicates are met.
template <class... Args>
@@ -600,7 +607,8 @@ public:
/// Compare the priority of this object and B.
///
/// Returns true if this object is more important than B.
- virtual bool isHigherPriorityThan(const InstructionPredicateMatcher &B) const {
+ virtual bool
+ isHigherPriorityThan(const InstructionPredicateMatcher &B) const {
return Kind < B.Kind;
};
@@ -631,7 +639,8 @@ public:
/// Compare the priority of this object and B.
///
/// Returns true if this object is more important than B.
- bool isHigherPriorityThan(const InstructionPredicateMatcher &B) const override {
+ bool
+ isHigherPriorityThan(const InstructionPredicateMatcher &B) const override {
if (InstructionPredicateMatcher::isHigherPriorityThan(B))
return true;
if (B.InstructionPredicateMatcher::isHigherPriorityThan(*this))
@@ -1118,7 +1127,8 @@ public:
void emitCxxActionStmts(raw_ostream &OS, RuleMatcher &Rule,
StringRef RecycleVarName) const override {
- OS << " constrainSelectedInstRegOperands(" << Name << ", TII, TRI, RBI);\n";
+ OS << " constrainSelectedInstRegOperands(" << Name
+ << ", TII, TRI, RBI);\n";
}
};
@@ -1165,14 +1175,16 @@ std::string RuleMatcher::defineInsnVar(r
return InsnVarName;
}
-StringRef RuleMatcher::getInsnVarName(const InstructionMatcher &InsnMatcher) const {
+StringRef
+RuleMatcher::getInsnVarName(const InstructionMatcher &InsnMatcher) const {
const auto &I = InsnVariableNames.find(&InsnMatcher);
if (I != InsnVariableNames.end())
return I->second;
llvm_unreachable("Matched Insn was not captured in a local variable");
}
-/// Emit a C++ initializer_list containing references to every matched instruction.
+/// Emit a C++ initializer_list containing references to every matched
+/// instruction.
void RuleMatcher::emitCxxCapturedInsnList(raw_ostream &OS) {
SmallVector<StringRef, 2> Names;
for (const auto &Pair : InsnVariableNames)
@@ -1425,7 +1437,8 @@ Expected<InstructionMatcher &> GlobalISe
InsnMatcher.addPredicate<InstructionOpcodeMatcher>(
&Target.getInstruction(RK.getDef("G_CONSTANT")));
} else
- return failedImport("Unable to deduce gMIR opcode to handle Src (which is a leaf)");
+ return failedImport(
+ "Unable to deduce gMIR opcode to handle Src (which is a leaf)");
} else {
auto SrcGIOrNull = findNodeEquiv(Src->getOperator());
if (!SrcGIOrNull)
@@ -1458,7 +1471,8 @@ Expected<InstructionMatcher &> GlobalISe
OperandMatcher &OM = InsnMatcher.addOperand(OpIdx++, "", TempOpIdx);
OM.addPredicate<LiteralIntOperandMatcher>(SrcIntInit->getValue());
} else
- return failedImport("Unable to deduce gMIR opcode to handle Src (which is a leaf)");
+ return failedImport(
+ "Unable to deduce gMIR opcode to handle Src (which is a leaf)");
} else {
// Match the used operands (i.e. the children of the operator).
for (unsigned i = 0, e = Src->getNumChildren(); i != e; ++i) {
@@ -1666,7 +1680,8 @@ Expected<BuildMIAction &> GlobalISelEmit
if (!Dst->getChild(0)->isLeaf())
return failedImport("EXTRACT_SUBREG child #1 is not a leaf");
- if (DefInit *SubRegInit = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue())) {
+ if (DefInit *SubRegInit =
+ dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue())) {
CodeGenRegisterClass *RC = CGRegs.getRegClass(
getInitValueAsRegClass(Dst->getChild(0)->getLeafValue()));
CodeGenSubRegIndex *SubIdx = CGRegs.getSubRegIdx(SubRegInit->getDef());
@@ -1817,7 +1832,8 @@ Expected<RuleMatcher> GlobalISelEmitter:
if (!Dst->getChild(0)->isLeaf())
return failedImport("EXTRACT_SUBREG operand #0 isn't a leaf");
- // We can assume that a subregister is in the same bank as it's super register.
+ // We can assume that a subregister is in the same bank as it's super
+ // register.
DstIOpRec = getInitValueAsRegClass(Dst->getChild(0)->getLeafValue());
if (DstIOpRec == nullptr)
@@ -1826,7 +1842,8 @@ Expected<RuleMatcher> GlobalISelEmitter:
} else if (DstIOpRec->isSubClassOf("RegisterOperand"))
DstIOpRec = DstIOpRec->getValueAsDef("RegClass");
else if (!DstIOpRec->isSubClassOf("RegisterClass"))
- return failedImport("Dst MI def isn't a register class" + to_string(*Dst));
+ return failedImport("Dst MI def isn't a register class" +
+ to_string(*Dst));
OperandMatcher &OM = InsnMatcher.getOperand(OpIdx);
OM.setSymbolicName(DstIOperand.Name);
@@ -1898,8 +1915,10 @@ Expected<RuleMatcher> GlobalISelEmitter:
const auto &SrcRCDstRCPair =
SrcRC->getMatchingSubClassWithSubRegs(CGRegs, SubIdx);
assert(SrcRCDstRCPair->second && "Couldn't find a matching subclass");
- M.addAction<ConstrainOperandToRegClassAction>("NewI", 0, *SrcRCDstRCPair->second);
- M.addAction<ConstrainOperandToRegClassAction>("NewI", 1, *SrcRCDstRCPair->first);
+ M.addAction<ConstrainOperandToRegClassAction>("NewI", 0,
+ *SrcRCDstRCPair->second);
+ M.addAction<ConstrainOperandToRegClassAction>("NewI", 1,
+ *SrcRCDstRCPair->first);
// We're done with this pattern! It's eligible for GISel emission; return
// it.
@@ -2007,8 +2026,10 @@ void GlobalISelEmitter::run(raw_ostream
<< "InstructionSelector::selectImpl(MachineInstr &I) const {\n"
<< " MachineFunction &MF = *I.getParent()->getParent();\n"
<< " const MachineRegisterInfo &MRI = MF.getRegInfo();\n"
- << " // FIXME: This should be computed on a per-function basis rather than per-insn.\n"
- << " AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, &MF);\n"
+ << " // FIXME: This should be computed on a per-function basis rather "
+ "than per-insn.\n"
+ << " AvailableFunctionFeatures = computeAvailableFunctionFeatures(&STI, "
+ "&MF);\n"
<< " const PredicateBitset AvailableFeatures = getAvailableFeatures();\n";
for (auto &Rule : Rules) {
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