[PATCH] D34077: DAGCombine: Combine BUILD_VECTOR to TRUNCATE

[Zvi Rackover via Phabricator via llvm-commits]

zvi added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:14272
+      (VT.getScalarSizeInBits() * Stride > 64))
+    return SDValue();
+
----------------
zvi wrote:
> RKSimon wrote:
> > Check for ISD::TRUNCATE legality, this might even help ARM?
> Thanks for suggesting that. Will give it a try.
The X86 backend does not set any truncates as legal; all truncates are lowered using custom lowering, so i don't see how we can use this as a criteria  for applying the combine.


https://reviews.llvm.org/D34077