[PATCH] D34559: [X86][DAG] Switch X86 Target to post-legalized store merge

[Nirav Dave via Phabricator via llvm-commits]

niravd created this revision.

Move store merge to happen after intrinsic lowering to allow
lowered stores to be merged.

To get storemerge to catch semi-trivial cases , e.g, 
merge_vec_element_store and merge_vec_element_store in
CodeGen/X86/MergeConsecutiveStore.ll,  the lowering optimization
from extractps 0 to movss was disabled as it dramatically increased 
complexity of the necessary matching logic in store merge. Ideally this
can be introduced in an alternative way.


https://reviews.llvm.org/D34559

Files:
  include/llvm/Target/TargetLowering.h
  lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  test/CodeGen/X86/2011-10-19-widen_vselect.ll
  test/CodeGen/X86/MergeConsecutiveStores.ll
  test/CodeGen/X86/avx1-logical-load-folding.ll
  test/CodeGen/X86/avx512-intrinsics.ll
  test/CodeGen/X86/bigstructret.ll
  test/CodeGen/X86/bitcast-i256.ll
  test/CodeGen/X86/constant-combines.ll
  test/CodeGen/X86/extract-store.ll
  test/CodeGen/X86/fma-scalar-memfold.ll
  test/CodeGen/X86/fold-vector-sext-crash2.ll
  test/CodeGen/X86/legalize-shl-vec.ll
  test/CodeGen/X86/merge-consecutive-loads-128.ll
  test/CodeGen/X86/merge-store-partially-alias-loads.ll
  test/CodeGen/X86/no-sse2-avg.ll
  test/CodeGen/X86/sse4a-upgrade.ll
  test/CodeGen/X86/stdarg.ll
  test/CodeGen/X86/stores-merging.ll
  test/CodeGen/X86/vec_fptrunc.ll
  test/CodeGen/X86/vector-shuffle-256-v4.ll
  test/CodeGen/X86/widen_arith-6.ll
  test/CodeGen/X86/widen_conv-3.ll
  test/CodeGen/X86/widen_conv-4.ll
  test/CodeGen/X86/widen_shuffle-1.ll

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